c9a7d4d927
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com> |
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|---|---|---|
| .. | ||
| Makefile | ||
| README.md | ||
| system_bd.tcl | ||
| system_constr.xdc | ||
| system_constr_1sdi.xdc | ||
| system_constr_2sdi.xdc | ||
| system_constr_4sdi.xdc | ||
| system_constr_8sdi.xdc | ||
| system_project.tcl | ||
| system_top.v | ||
README.md
EVAL-AD463X_FMCZ HDL reference design
Building the design
The design supports almost all the digital interface modes of AD4630-24, a new bit stream should be generated each time when the targeted configuration changes.
Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR data capture and capture zone 2.
Building attributes
| Attribute name | Valid values |
|---|---|
| CLK_MODE | 0 - SPI / 1 - Echo-clock or Master clock |
| NUM_OF_SDI | 1 - Interleaved / 2 - 1LPC / 4 - 2LPC / 8 - 4LPC |
| CAPTURE_ZONE | 1 - negedge of BUSY / 2 - next posedge of CNV |
| DDR_EN | 0 - MISO runs on SDR / 1 - MISO runs on DDR |
Example: make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
Documentation
https://wiki.analog.com/resources/eval/user-guides/ad463x/hdl