165 lines
5.2 KiB
Verilog
165 lines
5.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output [13:0] ddr3_addr,
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output [ 2:0] ddr3_ba,
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output ddr3_cas_n,
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output [ 0:0] ddr3_ck_n,
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output [ 0:0] ddr3_ck_p,
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output [ 0:0] ddr3_cke,
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output [ 0:0] ddr3_cs_n,
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output [ 7:0] ddr3_dm,
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inout [63:0] ddr3_dq,
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inout [ 7:0] ddr3_dqs_n,
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inout [ 7:0] ddr3_dqs_p,
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output [ 0:0] ddr3_odt,
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output ddr3_ras_n,
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output ddr3_reset_n,
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output ddr3_we_n,
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output phy_reset_n,
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output phy_mdc,
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inout phy_mdio,
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output phy_tx_clk,
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output phy_tx_ctrl,
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output [ 3:0] phy_tx_data,
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input phy_rx_clk,
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input phy_rx_ctrl,
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input [ 3:0] phy_rx_data,
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output fan_pwm,
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inout [ 6:0] gpio_lcd,
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inout [12:0] gpio_bd,
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output iic_rstn,
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inout iic_scl,
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inout iic_sda,
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output hdmi_out_clk,
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output hdmi_hsync,
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output hdmi_vsync,
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output hdmi_data_e,
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output [23:0] hdmi_data,
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output spdif);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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// default logic
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assign mgt_clk_sel = 2'd0;
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assign fan_pwm = 1'b1;
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assign iic_rstn = 1'b1;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_sw_led (
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.dio_t (gpio_t[12:0]),
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.dio_i (gpio_o[12:0]),
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.dio_o (gpio_i[12:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.gpio_lcd_tri_io (gpio_lcd),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio0_i (gpio_i[31:0]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio1_i (gpio_i[63:32]),
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.hdmi_24_data (hdmi_data),
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.hdmi_24_data_e (hdmi_data_e),
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.hdmi_24_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_24_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.mb_intr_06 (1'b0),
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.mb_intr_12 (1'b0),
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.mb_intr_13 (1'b0),
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.mb_intr_14 (1'b0),
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.mb_intr_15 (1'b0),
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.mdio_mdio_io (phy_mdio),
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.mdio_mdc (phy_mdc),
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.phy_rst_n (phy_reset_n),
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.rgmii_rd (phy_rx_data),
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.rgmii_rx_ctl (phy_rx_ctrl),
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.rgmii_rxc (phy_rx_clk),
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.rgmii_td (phy_tx_data),
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.rgmii_tx_ctl (phy_tx_ctrl),
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.rgmii_txc (phy_tx_clk),
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.spdif (spdif),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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