714 lines
22 KiB
Markdown
Executable File
714 lines
22 KiB
Markdown
Executable File
# HDL Coding Guidelines
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## Introduction
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This document contains coding and documentation guidelines which must be
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followed by all HDL projects. The purpose of this document is to establish
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a set of rules that specify the layout, naming conventions and some general
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coding practices for the HDL modules implementation. Specific HDL coding practices
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meant to obtain maximum performance from a FPGA design are described by external
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documents such as [1] and [2] and are not included in this document.
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There are two types of rules: *should* and *must* rules
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* *Should* rules are advisory rules. They suggest the recommended way of doing
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things.
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* *Must* rules are mandatory requirements.
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The coding rules are intended to be applied to HDL modules written using VHDL
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or Verilog.
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When an external IP is used, the naming conventions practiced by the IP *should* be kept,
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even if they do not match the rules specified in this document.
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## Coding Style
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### A. Layout
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**A1**: For indentation, spaces **must** be used instead of tabs. This allows
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the code to be properly visualized by any editor. **Do not** leave spaces at
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the end of a line. The following editor settings **must** be used:
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*Tab Size*: 2, *Indent Size*: 2
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**A2**: One white space **must** be inserted around operators, such as
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=, ==, &&, ||, &, |, ^, etc.
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#### Example:
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##### Incorrect:
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```verilog
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if((my_signal1==1'b0)&&(my_bus[3:0]==4'd5))
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```
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##### Correct:
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```verilog
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if ((my_signal == 1'b0) && (my_bus[3:0] == 4'd5))
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```
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**A3**: The _always_ block *should* have a space before **@** symbol.
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#### Example:
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##### Incorrect:
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```verilog
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always@(posedge clk) begin
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...
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end
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```
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##### Correct:
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```verilog
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always @(posedge clk) begin
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...
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end
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```
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**A4**: The Verilog ``begin``/``end`` block **must** always be used, even if there is
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only one statement. This makes adding lines of code much easier and with fewer errors.
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**A5**: Indentation levels **must** be used to show code nesting. Blank lines
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may be used as desired to improve code readability, but _not_ in all cases.
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#### Example:
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##### Incorrect:
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```verilog
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if (my_signal == 1'b0) begin
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if (my_bus[3:0]==4'd5) begin
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statement1;
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statement2;
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end
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statement3;
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statement4;
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end
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else
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statement5;
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```
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##### Correct:
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```verilog
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if (my_signal == 1'b0) begin
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if (my_bus[3:0] == 4'd5) begin
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statement1;
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statement2;
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end
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statement3;
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statement4;
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end else begin
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statement5;
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end
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```
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**A6**: In a ``case`` definition, indentation levels **must** be used to offset
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the statements that are encapsulated, but the use of blank lines can be used or
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omitted to best show the statement groupings (if really necessary). ``end`` should
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be indented as in the correct example.
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#### Example:
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##### Incorrect:
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```verilog
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case ( my_bus[3:0] )
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4'b0000 : my_signal1 = TRUE;
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4'b0001 : my_signal1 = FALSE;
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4'b0010 :
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begin
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my_signal1 = TRUE;
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my_signal2 = FALSE;
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end
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4'b0100 : my_signal2 = FALSE;
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default : my_signal1 = TRUE;
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endcase
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```
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##### Correct:
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```verilog
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case (my_bus[3:0])
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4'b0000: begin
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my_signal1 = TRUE;
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end
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4'b0001: begin
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my_signal1 = FALSE;
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end
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4'b0010: begin
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my_signal1 = TRUE;
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my_signal2 = FALSE;
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end
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4'b0100: begin
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my_signal2 = FALSE;
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end
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default: begin
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my_signal1 = TRUE;
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end
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endcase
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```
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**A7**: Alignment **should** be used in declarations, assignments, multi-line
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statements, and end of line comments. The code **must** be written in a tabular
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format.
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#### Example:
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##### Incorrect:
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```verilog
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reg[3:0] my_signal1; //description
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reg[31:0] my_decoded_signal1; //description
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reg[4:0] my_signal2, my_signal3; //description
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wire[2:0] my_select; //description
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```
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##### Correct:
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```verilog
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reg [ 3:0] my_signal1; //description
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reg [31:0] my_decoded_signal1; //description
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reg [ 4:0] my_signal2; //description
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reg my_signal3; //description
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wire [ 2:0] my_select; //description
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```
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**A8**: Parentheses **must** be used around all boolean statements and in
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complex equations, in order to force the order of operations and avoid confusion.
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Complex boolean expressions *should* be expressed as multi-line aligned statements.
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#### Example:
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##### Incorrect:
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```verilog
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if ((my_signal1 && your_signal1) || (my_signal2 && your_signal2) || (my_signal3 && your_signal3)) begin
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my_signal1 = TRUE;
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my_delayed_signal1 = !your_signal;
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end
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```
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##### Correct:
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```verilog
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if ((my_signal1 && your_signal1) ||
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(my_signal2 && your_signal2) ||
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(my_signal3 && your_signal3)) begin
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my_signal1 = TRUE;
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my_delayed_signal1 = !your_signal;
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end
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```
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**A9**: A line **must** not contain more than one statement. **Do not** concatenate
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multiple statements on the same line.
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#### Example:
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##### Incorrect:
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```verilog
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upper_en = (p5type && xadr1[0]); lower_en = (p5type && !xadr1[0]);
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```
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##### Correct:
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```verilog
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upper_en = (p5type && xadr1[0]);
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lower_en = (p5type && !xadr1[0]);
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```
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**A10**: In module instances:
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**A10.1**: **All** parameters and ports, **must** be written on a separate line,
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even if there are few of them or their names are short.
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#### Example:
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##### Incorrect:
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```verilog
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my_module #(.PARAMETER1 (PARAMETER1)) i_my_module (.clk (clk));
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```
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##### Correct:
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```verilog
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my_module #(
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.PARAMETER1 (PARAMETER1)
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) i_my_module (
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.clk (clk));
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```
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**A10.2**: When instantiating a module, the label of the module instance **must** be
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on a separate line, with the closing parenthesis of the parameters list (if that's
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the case) and the opening parenthesis of the ports list. The closing parenthesis of
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the ports list must be right next to the last parenthesis of the last port.
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#### Example:
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```verilog
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my_module #(
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.PARAMETER1 (PARAMETER1),
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.PARAMETER2 (PARAMETER2)
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) i_my_module (
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.clk (clk),
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.rst (rst),
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.data_in (data_in),
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.en (en),
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.response_out (response_out));
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```
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**A10.3**: Commented parts of code **must** not be added to the master branch (i.e if,
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case, module instances, etc).
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**A11**: In module declarations:
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**A11.1**: Verilog modules **must** use Verilog-2001 style parameter
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declarations. This increases legibility and consistency.
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#### Example:
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```verilog
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module my_module #(
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parameter PARAMETER1 = 0
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) (
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input clk,
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input rst,
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input [7:0] data_0,
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input [7:0] data_1,
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input enable,
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input valid,
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// interface 1
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input interf1_clk,
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inout interf1_some_signal,
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output [15:0] interf1_data_i,
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output [15:0] interf1_data_q,
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// interface 2
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input interf2_some_signal,
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output interf2_data_out
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);
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```
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**A11.2**: Comments are allowed inside a module declaration **only** for separating
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the interfaces by specifying the name and giving supplementary explanations.
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**A11.3**: When declaring a module, the closing parenthesis of the parameters list
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**must** be on the same line with the last parameter and with the opening parenthesis
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of the ports list (as shown in the correct examples).
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**A11.4**: After ``endmodule`` there **must** be only one newline, and nothing else after.
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**A12**: Ports **must** be indicated individually; that is, one port per line
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must be declared, using the direction indication and data type with each port.
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**A13**: Signals and variables **must** be declared individually; that is,
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one signal/variable per line **must** be declared.
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**A14**: All ports and signals **must** be grouped by interface. Group ports
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declaration by direction starting with input, inout and output ports.
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**A15**: The clock and reset ports **must** be declared first.
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**A16**: Verilog wires and registers declarations **must** be grouped in
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separate sections. **Firstly** register types and then wire types.
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**A17**: The source files *should* have the format shown in Annex 1 for
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Verilog code and Annex 2 for VHDL code.
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### B. Naming Conventions
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**B1**: All the names in the source code **must** be written in English.
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**B2**: Names **must** start with a letter, be composed of alphanumeric
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characters or underscores **[A-Z, a-z, 0-9,_]**.
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**B3**: All modules, signal and register names **must** be lower case,
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delimited by underscores “_”.
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#### Example:
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```verilog
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module my_module (
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input ena_fft,
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input ena_mdi,
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input fft_in,
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output mdi_out,
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output [15:0] my_signal1
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);
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```
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**B4**: A file **must** contain a single module. File name **must** be the same
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as the module name. For sub-modules the name **must** be composed in the following
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way:
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```
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<top_module_name>_<sub_module_description>.
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```
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**B5**: All parameter names **must** be upper case with underscore delimiters.
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**B6**: Signals names *should* be composed in the following way:
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```
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[interface|clock domain]_<signal_name>[_ns][_l][_p][_n][_m1][_m2][_s]
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```
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The suffix component may be used as described below and, in the case of multiple
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suffixes being used in the same signal name, must only be used in the order
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specified in the signal name descriptions above.
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**_ns** - State machine next state.
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**_l** - Latch output. Optional for signals leaving top-level module or
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sub-module, required for signals internal to a module
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**_p** - Positive side of differential signal.
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**_n** - Negative side of differential signal.
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- Active low signal. Can also be used for negative side of differential
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signal.
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**_m1/_m2** - Used to describe registers synchronizers (e.g. up_ack_m1, up_ack_m2)
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**_s** - Used to qualify wires/signals (e.g. up_ack_s)
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This rule is useful for complex modules where it is possible to incorrectly use
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a signal if its name does not contain a suffix to specify its purpose. Generally
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this rule can lead to an unnecessary naming complexity and thus can be
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overlooked unless it is absolutely necessary.
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**B7**: Ports names *should* be composed in the following way:
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```
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<interface_name>_<port_name>[_clk][_rst][_p][_n]
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```
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**_clk** - Clock signal. Exception: Signals whose names obviously indicate
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clocks (e.g. system_clock or clk32m), or when specifying a clock with a certain
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frequency (in this case clk *should* be used as a prefix: e.g. clk_625mhz)
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**_rst / _rstn** - Reset signal (e.g. module_rst). Exception: Signals whose
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names obviously indicate resets.
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**_p** - Positive side of differential signal.
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**_n** - Active low signal. Can also be used for negative side of differential
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signal.
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**B8**: Global text macros specified by the ``‘define`` directive **must** be
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preceded with the top-level module name, as in:
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```
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<top_level_module_name>_<text macro name>
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```
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**B9**: Consistent usage in the spelling and naming style of nets and
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variables **must** be used throughout the design.
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**B10**: Abbreviations used in a module **must** be documented and uncommon
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abbreviations *should* be avoided.
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**B11**: Reset and clock names **must** remain the same across hierarchy.
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### C. Comments
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**C1**: Comments **must** be used to describe the functionality of the HDL
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code. Liberal use of comments is strongly encouraged. Adding obvious comments
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is discouraged. Basically, extensive comments that proceed blocks of code,
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coupled with sparse back references, guide the reader through the code.
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**C2**: Each functional section of the code *should* be preceded by comments
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describing the code's intent and function.
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**C3**: Unusual or non-obvious implementations **must** be explained and their
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limitations documented with a comment.
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**C4**: Each port declaration *should* have a descriptive comment, **only** on the
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preceding line.
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**C5**: Other declarations, such as regs, wires, local parameters, *should* have a
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descriptive comment. Either on the same line (discouraged), or on the preceding line.
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This rule is optional for auto-generated code.
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**C6**: All synthesis-specific directives **must** be documented where used,
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identifying the reason they are used, the tool and the directive used.
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**C7**: The comments inserted in the code **must** comply with the format
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shown in Annex 1 for Verilog code and Annex 2 for VHDL code.
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### D. General
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**D1**: A file **must** contain a single module.
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**D2**: A file **must** contain either: digital-only Verilog code (files with
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.v extension); analog-only Verilog code (files with .va or .vams extension); or
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mixed-signal Verilog code (files with .vams extension).
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**D3**: Symbolic constants (local parameter) *should* be used for register
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field values rather than fixed numerical constants. The fields may be one or
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more bits or the entire register.
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**D4**: Port connection width **must** match. In module instantiations, nets
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connected to ports must have the same width as the respective port declaration.
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**D5**: The ranges in both the vector port declaration and the net/variable
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declaration **must** be equal.
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**D6**: Operands sizes **must** match. No expression may have its size
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implicitly extended or reduced. In a ``case`` statement, all the ``case`` item
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expressions and the ``case`` expression must have the same size.
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**D7**: Combinational logic **must** be specified completely (i.e., a value
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must be assigned to the logic outputs for all input combinations). In a construct
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derived from either a ``case`` or an ``if`` statement, the outputs may be assigned
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default values before the ``case`` or ``if`` statement, and then the logic is completely
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specified.
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**D8**: The sensitivity list of Verilog ``always`` and VHDL ``process`` constructs
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**must** be completely specified.
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**D9**: Modules **must** be instantiated with full I/O – all port names and
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signal connections must be listed on all module instantiations. Do not leave any
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input ports open (even if they are unused), always tie them to 0 or 1. Leave
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unused outputs open **but do** list them.
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**D10**: A ``timescale`` directive that is best for simulation *should* be used
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in Verilog modules.
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**D11**: Compile warnings **must** be treated as potential errors and *should*
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always try to be resolved. In case a warning is not resolved its cause and
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effects must be fully understood.
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**D12**: Critical warnings **must** be treated and fixed.
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**D13**: Each file **must** contain a license header, and when changes are made
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to a file, when making a PR, the year _should_ be updated to the current year.
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## 3. Annexes
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### Annex 1 Verilog file format
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```verilog
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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'timescale 1ns/100ps
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module prescaler #(
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//Range = 1-16
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parameter FIRST_PARAMETER = 8,
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//Range = N/A
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parameter SECOND_PARAMETER = 12
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) (
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input core_32m_clk, // 32 MHz clock
|
||
input system_clk, // system clock
|
||
input scan_mode_test, // scan mode clock
|
||
input reset_n, // active low hard reset, synch w/
|
||
// system_clk
|
||
output reg div16_clk, // input clock divided by 16
|
||
output reg div16_clk_n // input clock divided by 16 and inverted
|
||
);
|
||
// Local Parameters
|
||
|
||
// Registers Declarations
|
||
|
||
reg [3:0] count; // 4-bit counter to make clock divider
|
||
reg [3:0] count1; // 4-bit counter to make clock divider
|
||
|
||
// Wires Declarations
|
||
|
||
wire [3:0] count1_ns; // clock divider next state input
|
||
|
||
// Functions Definitions
|
||
|
||
// This block updates the internal counter
|
||
always @(posedge core_32m_clk or negedge reset_n) begin
|
||
if (!reset_n) begin
|
||
count <= 4’b0000;
|
||
end else begin
|
||
// update counter
|
||
count <= count + 4’b0001;
|
||
end
|
||
end
|
||
|
||
// This block updates the output clock signals
|
||
always @(scan_mode_test or system_clk or count) begin
|
||
if (!scan_mode_test) begin
|
||
// normal operation clock assign
|
||
div16_clk = count[3];
|
||
div16_clk_n = ~count[3];
|
||
end else begin
|
||
// scan mode clock assign
|
||
div16_clk = system_clk;
|
||
div16_clk_n = system_clk;
|
||
end
|
||
end
|
||
|
||
// Modules Instantiations
|
||
|
||
endmodule
|
||
```
|
||
|
||
### Annex 2 VHDL file format
|
||
|
||
```vhdl
|
||
-- ***************************************************************************
|
||
-- ***************************************************************************
|
||
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||
--
|
||
-- In this HDL repository, there are many different and unique modules, consisting
|
||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||
-- developed independently, and may be accompanied by separate and unique license
|
||
-- terms.
|
||
--
|
||
-- The user should read each of these license terms, and understand the
|
||
-- freedoms and responsabilities that he or she has by using this source/core.
|
||
--
|
||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||
-- A PARTICULAR PURPOSE.
|
||
--
|
||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||
-- of this file, are permitted under one of the following two license terms:
|
||
--
|
||
-- 1. The GNU General Public License version 2 as published by the
|
||
-- Free Software Foundation, which can be found in the top level directory
|
||
-- of this repository (LICENSE_GPL2), and also online at:
|
||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||
--
|
||
-- OR
|
||
--
|
||
-- 2. An ADI specific BSD license, which can be found in the top level directory
|
||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
|
||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||
-- This will allow to generate bit files and not release the source code,
|
||
-- as long as it attaches to an ADI device.
|
||
--
|
||
-- ***************************************************************************
|
||
-- ***************************************************************************
|
||
|
||
entity prescaler is
|
||
Port (
|
||
core_32m_clk : in std_logic, -- 32 MHz clock
|
||
system_clk : in std_logic, -- system clock
|
||
scan_mode_test : in std_logic, -- scan mode clock
|
||
reset_n : in std_logic, -- active low hard reset, synch
|
||
-- w/ system_clock
|
||
div16_clk : out std_logic, -- input clock divided by 16
|
||
div16_clk_n : out std_logic -- input clock divided by 16
|
||
-- and inverted
|
||
);
|
||
end prescaler;
|
||
|
||
architecture Behavioral of prescaler is
|
||
|
||
-- Components Declarations
|
||
|
||
-- Local Types Declarations
|
||
|
||
-- Constants Declarations
|
||
|
||
-- Signals Declarations
|
||
signal count : std_logic_vector(3 downto 0); -- 4-bit counter to
|
||
-- make clock divider
|
||
signal count_ns : std_logic_vector(3 downto 0); -- clock divider next
|
||
-- state input
|
||
|
||
-- Module Implementation
|
||
begin
|
||
|
||
-- This process updates the internal counter
|
||
process(core_32m_clk)
|
||
begin
|
||
if (rising_edge(core_32m_clk)) then
|
||
if (reset_n = '0') then
|
||
-- reset counter
|
||
count <= "0000";
|
||
else
|
||
-- update counter
|
||
count <= count + "0001";
|
||
end if;
|
||
end if;
|
||
end process;
|
||
|
||
-- This process updates the output clock signals
|
||
process(scan_mode_test, system_clk, count)
|
||
begin
|
||
if (scan_mode_test = '0') then
|
||
-- normal operation clock assign
|
||
div16_clk <= count(3);
|
||
div16_clk_n <= not count(3);
|
||
else
|
||
-- scan mode clock assign
|
||
div16_clk <= system_clk;
|
||
div16_clk_n <= system_clk;
|
||
end if;
|
||
end process;
|
||
|
||
end Behavioral;
|
||
```
|
||
|
||
## 4. References
|
||
|
||
[ 1] Philippe Garrault, Brian Philofsky, “HDL Coding Practices to Accelerate
|
||
Design Performance”, Xilinx, 2006, Online document available at:
|
||
http://www.xilinx.com/support/documentation/white_papers/wp231.pdf
|
||
|
||
[ 2] Peter Chambers, “The Ten Commandments of Excellent Design”, VLSI Technology,
|
||
1997, Online document available at:
|
||
http://www.asic-world.com/code/verilog_tutorial/peter_chambers_10_commandments.pdf
|
||
|
||
[ 3] “Verilog Coding Techniques, v3.2”, Freescale Semiconductor, 2005, Online
|
||
document available at:
|
||
http://courses.cit.cornell.edu/ece576/Verilog/FreescaleVerilog.pdf
|
||
|
||
[ 4] Jane Smith, “Verilog Coding Guidelines, Rev. B”, Cisco Systems, 2000, Online
|
||
document available at: http://www.engr.sjsu.edu/cpham/VERILOG/VerilogCodingStyle.pdf
|
||
|
||
[1]: http://www.xilinx.com/support/documentation/white_papers/wp231.pdf
|
||
[2]: http://www.asic-world.com/code/verilog_tutorial/peter_chambers_10_commandments.pdf
|
||
|