801 lines
19 KiB
Plaintext
801 lines
19 KiB
Plaintext
TITLE
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DAC Common (axi_ad)
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DAC_COMMON
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0010
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REG_RSTN
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DAC Interface Control & Status
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ENDREG
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FIELD
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[2] 0x0
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CE_N
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RW
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Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of
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the module to control clock enables
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ENDFIELD
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FIELD
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[1] 0x0
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MMCM_RSTN
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RW
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MMCM reset only (required for DRP access).
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Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
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ENDFIELD
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FIELD
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[0] 0x0
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RSTN
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RW
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Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0011
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REG_CNTRL_1
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DAC Interface Control & Status
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ENDREG
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FIELD
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[0] 0x0
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SYNC
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RW
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Setting this bit synchronizes channels within a DAC, and across multiple instances.
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This bit self clears.
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ENDFIELD
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FIELD
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[1] 0x0
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EXT_SYNC_ARM
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RW
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Setting this bit will arm the trigger mechanism sensitive to an external sync signal.
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Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances.
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This bit has an effect only the EXT_SYNC synthesis parameter is set.
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This bit self clears.
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ENDFIELD
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FIELD
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[2] 0x0
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EXT_SYNC_DISARM
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RW
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Setting this bit will disarm the trigger mechanism sensitive to an external sync signal.
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This bit has an effect only the EXT_SYNC synthesis parameter is set.
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This bit self clears.
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ENDFIELD
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FIELD
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[8] 0x0
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MANUAL_SYNC_REQUEST
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RW
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Setting this bit will issue an external sync event if it is hooked up inside the fabric.
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This bit has an effect only the EXT_SYNC synthesis parameter is set.
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This bit self clears.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0012
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REG_CNTRL_2
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DAC Interface Control & Status
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ENDREG
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FIELD
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[16] 0x0
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SDR_DDR_N
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RW
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Interface type (1 represents SDR, 0 represents DDR)
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ENDFIELD
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FIELD
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[15] 0x0
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SYMB_OP
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RW
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Select data symbol format mode (0x1)
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ENDFIELD
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FIELD
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[14] 0x0
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SYMB_8_16B
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RW
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Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
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ENDFIELD
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FIELD
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[12:8] 0x0
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NUM_LANES[4:0]
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RW
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Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
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ENDFIELD
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FIELD
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[7] 0x0
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PAR_TYPE
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RW
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Select parity even (0x0) or odd (0x1).
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ENDFIELD
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FIELD
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[6] 0x0
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PAR_ENB
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RW
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Select parity (0x1) or frame (0x0) mode.
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ENDFIELD
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FIELD
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[5] 0x0
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R1_MODE
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RW
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Select number of RF channels 1 (0x1) or 2 (0x0).
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ENDFIELD
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FIELD
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[4] 0x0
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DATA_FORMAT
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RW
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Select data format 2's complement (0x0) or offset binary (0x1).
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NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[3:0] 0x00
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RESERVED[3:0]
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NA
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Reserved
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0013
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REG_RATECNTRL
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DAC Interface Control & Status
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ENDREG
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FIELD
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[7:0] 0x00
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RATE[7:0]
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RW
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The effective dac rate (the maximum possible rate is dependent on the interface clock).
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The samples are generated at 1/RATE of the interface clock.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0014
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REG_FRAME
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DAC Interface Control & Status
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ENDREG
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FIELD
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[0] 0x0
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FRAME
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RW
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The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1
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DCI clock period) pulse on the interface. This bit self clears.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0015
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REG_STATUS1
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DAC Interface Control & Status
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ENDREG
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FIELD
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[31:0] 0x00000000
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CLK_FREQ[31:0]
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RO
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Interface clock frequency. This is relative to the processor clock and in many cases is
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100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
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clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
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is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
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the same as the interface clock- software must consider device specific implementation
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parameters to calculate the final sampling clock.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0016
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REG_STATUS2
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DAC Interface Control & Status
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ENDREG
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FIELD
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[31:0] 0x00000000
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CLK_RATIO[31:0]
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RO
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Interface clock ratio - as a factor actual received clock. This is implementation specific
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and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0017
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REG_STATUS3
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DAC Interface Control & Status
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ENDREG
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FIELD
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[0] 0x0
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STATUS
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RO
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Interface status, if set indicates no errors. If not set, there
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are errors, software may try resetting the cores.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0018
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REG_DAC_CLKSEL
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DAC Interface Control & Status
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ENDREG
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FIELD
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[0] 0x0
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DAC_CLKSEL
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RW
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Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001A
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REG_SYNC_STATUS
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DAC Synchronization Status register
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ENDREG
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FIELD
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[0] 0x0
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DAC_SYNC_STATUS
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RO
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DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal
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This bit has an effect only the EXT_SYNC synthesis parameter is set.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001C
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REG_DRP_CNTRL
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DRP Control & Status
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ENDREG
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FIELD
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[28] 0x0
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DRP_RWN
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RW
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DRP read (0x1) or write (0x0) select (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[27:16] 0x00
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DRP_ADDRESS[11:0]
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RW
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DRP address, designs that contain more than one DRP accessible primitives
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have selects based on the most significant bits (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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RESERVED[15:0]
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RO
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Reserved for backwards compatibility
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001D
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REG_DRP_STATUS
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DAC Interface Control & Status
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ENDREG
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FIELD
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[17] 0x0
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DRP_LOCKED
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RO
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If set indicates the MMCM/PLL is locked
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ENDFIELD
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FIELD
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[16] 0x0
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DRP_STATUS
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RO
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If set indicates busy (access pending). The read data may not be valid if
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this bit is set (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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RESERVED[15:0]
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RO
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Reserved for backwards compatibility
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001E
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REG_DRP_WDATA
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DAC Interface Control & Status
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ENDREG
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FIELD
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[15:0] 0x0000
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DRP_WDATA[15:0]
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RW
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DRP write data (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001F
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REG_DRP_RDATA
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DAC Interface Control & Status
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ENDREG
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FIELD
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[15:0] 0x0000
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DRP_RDATA
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RO
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DRP read data (does not include GTX lanes).
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NOT-APPLICABLE if DRP_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0022
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REG_UI_STATUS
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User Interface Status
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ENDREG
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FIELD
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[1] 0x0
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UI_OVF
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RW1C
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User Interface overflow. If set, indicates an overflow occurred during data transfer at
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the user interface (FIFO interface). Software must write a 0x1 to clear this register
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bit.
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ENDFIELD
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FIELD
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[0] 0x0
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UI_UNF
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RW1C
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User Interface underflow. If set, indicates an underflow occurred during data transfer at
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the user interface (FIFO interface). Software must write a 0x1 to clear this register
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bit.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0028
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REG_USR_CNTRL_1
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DAC User Control & Status
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ENDREG
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FIELD
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[7:0] 0x00
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USR_CHANMAX[7:0]
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RW
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This indicates the maximum number of inputs for the channel data multiplexers. User may add
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different processing modules as inputs to the dac.
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NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x002E
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REG_DAC_GPIO_IN
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DAC GPIO inputs
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ENDREG
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FIELD
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[31:0] 0x00000000
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DAC_GPIO_IN[31:0]
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RO
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This reads auxiliary GPI pins of the DAC core
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x002F
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REG_DAC_GPIO_OUT
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DAC GPIO outputs
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ENDREG
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FIELD
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[31:0] 0x00000000
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DAC_GPIO_OUT[31:0]
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RW
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This controls auxiliary GPO pins of the DAC core
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NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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TITLE
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DAC Channel (axi_ad*)
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DAC_CHANNEL
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0100
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REG_CHAN_CNTRL_1
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[15:0] 0x0000
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DDS_SCALE_1[15:0]
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RW
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The DDS scale for tone 1. Defines the amplitude of the tone. The format is
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1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on
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16-bits, note that if you do use both channels and set both scale to 0x4000,
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it is over-range. The final output is (channel_1_fullscale * scale_1) +
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(channel_2 * scale_2).
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0101
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REG_CHAN_CNTRL_2
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[31:16] 0x0000
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DDS_INIT_1[15:0]
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RW
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The DDS phase initialization for tone 1. Defines the initial phase offset of
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the tone.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DDS_INCR_1[15:0]
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RW
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Defines the resolution of the phase accumulator. Its value can be defined by
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<m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the generated
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output frequency, and f_if is the frequency of the digital interface, and
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clock_ratio is the ratio between the sampling clock and the interface clock.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0102
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REG_CHAN_CNTRL_3
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[15:0] 0x0000
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DDS_SCALE_2[15:0]
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RW
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The DDS scale for tone 1. Defines the amplitude of the tone. The format is
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1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on
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16-bits, note that if you do use both channels and set both scale to 0x4000,
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it is over-range. The final output is (channel_1_fullscale * scale_1) +
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(channel_2 * scale_2).
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0103
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REG_CHAN_CNTRL_4
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[31:16] 0x0000
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DDS_INIT_2[15:0]
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RW
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The DDS phase initialization for tone 1. Defines the initial phase offset of
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the tone.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DDS_INCR_2[15:0]
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RW
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Defines the resolution of the phase accumulator. Its value can be defined by
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<m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the generated
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output frequency, and f_if is the frequency of the digital interface, and
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clock_ratio is the ratio between the sampling clock and the interface clock.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0104
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REG_CHAN_CNTRL_5
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[31:16] 0x0000
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DDS_PATT_2[15:0]
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RW
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The DDS data pattern for this channel.
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DDS_PATT_1[15:0]
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RW
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The DDS data pattern for this channel.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0105
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REG_CHAN_CNTRL_6
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[2] 0x0
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IQCOR_ENB
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RW
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if set, enables IQ correction.
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NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[1] 0x0
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DAC_LB_OWR
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RW
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If set, forces DAC_DDS_SEL to 0x8, loopback
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If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
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ENDFIELD
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FIELD
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[0] 0x0
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DAC_PN_OWR
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RW
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IF set, forces DAC_DDS_SEL to 0x09, device specific pnX
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If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0106
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REG_CHAN_CNTRL_7
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[3:0] 0x00
|
|
DAC_DDS_SEL[3:0]
|
|
RW
|
|
Select internal data sources (available only if the DAC supports it). \\
|
|
- 0x00: internal tone (DDS) \\
|
|
- 0x01: pattern (SED) \\
|
|
- 0x02: input data (DMA) \\
|
|
- 0x03: 0x00 \\
|
|
- 0x04: inverted pn7 \\
|
|
- 0x05: inverted pn15 \\
|
|
- 0x06: pn7 (standard O.150) \\
|
|
- 0x07: pn15 (standard O.150) \\
|
|
- 0x08: loopback data (ADC) \\
|
|
- 0x09: pnX (Device specific e.g. ad9361) \\
|
|
- 0x0A: Nibble ramp (Device specific e.g. adrv9001) \\
|
|
- 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \\
|
|
ENDFIELD
|
|
|
|
############################################################################################
|
|
############################################################################################
|
|
|
|
REG
|
|
0x0107
|
|
REG_CHAN_CNTRL_8
|
|
DAC Channel Control & Status (channel - 0)
|
|
ENDREG
|
|
|
|
FIELD
|
|
[31:16] 0x0000
|
|
IQCOR_COEFF_1[15:0]
|
|
RW
|
|
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value
|
|
and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used,
|
|
this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits).
|
|
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[15:0] 0x0000
|
|
IQCOR_COEFF_2[15:0]
|
|
RW
|
|
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value
|
|
and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient
|
|
and the format is 1.1.14 (sign, integer and fractional bits).
|
|
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
############################################################################################
|
|
############################################################################################
|
|
|
|
REG
|
|
0x0108
|
|
REG_USR_CNTRL_3
|
|
DAC Channel Control & Status (channel - 0)
|
|
ENDREG
|
|
|
|
FIELD
|
|
[25] 0x0
|
|
USR_DATATYPE_BE
|
|
RW
|
|
The user data type format- if set, indicates big endian (default is little endian).
|
|
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[24] 0x0
|
|
USR_DATATYPE_SIGNED
|
|
RW
|
|
The user data type format- if set, indicates signed (2's complement) data (default is unsigned).
|
|
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[23:16] 0x00
|
|
USR_DATATYPE_SHIFT[7:0]
|
|
RW
|
|
The user data type format- the amount of right shift for actual samples within the total number
|
|
of bits.
|
|
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[15:8] 0x00
|
|
USR_DATATYPE_TOTAL_BITS[7:0]
|
|
RW
|
|
The user data type format- number of total bits used for a sample. The total number of bits must
|
|
be an integer multiple of 8 (byte aligned).
|
|
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[7:0] 0x00
|
|
USR_DATATYPE_BITS[7:0]
|
|
RW
|
|
The user data type format- number of bits in a sample. This indicates the actual sample data bits.
|
|
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
############################################################################################
|
|
############################################################################################
|
|
|
|
REG
|
|
0x0109
|
|
REG_USR_CNTRL_4
|
|
DAC Channel Control & Status (channel - 0)
|
|
ENDREG
|
|
|
|
FIELD
|
|
[31:16] 0x0000
|
|
USR_INTERPOLATION_M[15:0]
|
|
RW
|
|
This holds the user interpolation M value of the channel that is currently being selected on
|
|
the multiplexer above. The total interpolation factor is of the form M/N.
|
|
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[15:0] 0x0000
|
|
USR_INTERPOLATION_N[15:0]
|
|
RW
|
|
This holds the user interpolation N value of the channel that is currently being selected on
|
|
the multiplexer above. The total interpolation factor is of the form M/N.
|
|
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
|
|
ENDFIELD
|
|
|
|
############################################################################################
|
|
############################################################################################
|
|
|
|
REG
|
|
0x010A
|
|
REG_USR_CNTRL_5
|
|
DAC Channel Control & Status (channel - 0)
|
|
ENDREG
|
|
|
|
FIELD
|
|
[0] 0x0
|
|
DAC_IQ_MODE[0]
|
|
RW
|
|
Enable complex mode. In this mode the driven data to the DAC must be a sequence
|
|
of I and Q sample pairs.
|
|
ENDFIELD
|
|
|
|
FIELD
|
|
[1] 0x0
|
|
DAC_IQ_SWAP[1]
|
|
RW
|
|
Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
|
|
ENDFIELD
|
|
|
|
############################################################################################
|
|
############################################################################################
|
|
|
|
REG
|
|
0x0110
|
|
REG_*
|
|
Channel 1, similar to registers 0x100 to 0x10f.
|
|
ENDREG
|
|
|
|
REG
|
|
0x0120
|
|
REG_*
|
|
Channel 2, similar to registers 0x100 to 0x10f.
|
|
ENDREG
|
|
|
|
REG
|
|
0x01F0
|
|
REG_*
|
|
Channel 15, similar to registers 0x100 to 0x10f.
|
|
ENDREG
|
|
|
|
############################################################################################
|
|
############################################################################################
|