Istvan Csomortani 91b199a907 s10soc: Add new feature for ad_cpu_interconnect ... If we have a lot of peripherals connected to the CPU's memory interface, the generated interconnect can grow to much decreasing the timing margin. One solution is to group the peripherals by its interface types and functions and use bridges to connect them to the memory interface. This commit adds the possibility to insert an Avalon Memory Mapped bridge when we create the connection between the peripheral and CPU. Should be used just with Avalaon Memory Mapped interfaces.		2020-09-09 14:15:37 +03:00
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s10soc_system_assign.tcl	stratix10soc: Initial commit of base design	2020-09-09 14:15:37 +03:00
s10soc_system_qsys.tcl	s10soc: Add new feature for ad_cpu_interconnect	2020-09-09 14:15:37 +03:00