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laurent-19 6b94259a52 projects/common: Add system_top _project templates 
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct code and modify according to guidelines

* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct/Add missing wrapper ports and iobufs

* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

ac701/system_top.v: Change top based on previous projects

 * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

projects/common: Modify templates to build without errors

* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
	 system_project: Added adi_board, adiobuf sourcing
	 system_top: Removed hdmi, i2c, fanpwm, spdif ports
		     according to base design
* c5soc: Added version settings
	 Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
	    system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
	 Removed unnecessary ports

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Delete microzed vmk_es templates

* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 		2022-09-20 17:00:49 +03:00
..
a10gx projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
a10soc projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
ac701 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
c5soc projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
coraz7s projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
de10nano projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
intel scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
kc705 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
kcu105 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
microzed projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
s10soc projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
vc707 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
vc709 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
vck190 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
vcu118 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
vcu128 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
vmk180 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
vmk180_es1 common/vmk180_es1: Initial version 2021-10-05 14:09:51 +03:00
xilinx data_offload: Refactor core 2022-04-28 14:31:32 +03:00
zc702 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
zc706 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
zcu102 projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
zed projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00