58 lines
2.2 KiB
Verilog
Executable File
58 lines
2.2 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2019 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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`timescale 1ns / 1ps
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module sysid_rom #(
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parameter ROM_WIDTH = 32,
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parameter ROM_ADDR_BITS = 6,
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parameter PATH_TO_FILE = "path_to_mem_init_file"
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) (
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input clk,
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input [ROM_ADDR_BITS-1:0] rom_addr,
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output reg [ROM_WIDTH-1:0] rom_data
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);
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reg [ROM_WIDTH-1:0] lut_rom [(2**ROM_ADDR_BITS)-1:0];
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initial begin
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$readmemh(PATH_TO_FILE, lut_rom, 0, (2**ROM_ADDR_BITS)-1);
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end
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always @(posedge clk) begin
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rom_data = lut_rom[rom_addr];
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end
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endmodule
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