267 lines
8.5 KiB
Verilog
Executable File
267 lines
8.5 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_fifo2s (
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// fifo interface
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m_rst,
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m_clk,
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m_wr,
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m_wdata,
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m_wovf,
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axi_mwr,
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axi_mwdata,
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axi_mwovf,
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axi_mwpfull,
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// axi interface
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axi_clk,
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axi_resetn,
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axi_awvalid,
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axi_awid,
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axi_awburst,
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axi_awlock,
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axi_awcache,
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axi_awprot,
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axi_awqos,
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axi_awuser,
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axi_awlen,
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axi_awsize,
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axi_awaddr,
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axi_awready,
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axi_wvalid,
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axi_wdata,
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axi_wstrb,
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axi_wlast,
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axi_wuser,
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axi_wready,
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axi_bvalid,
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axi_bid,
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axi_bresp,
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axi_buser,
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axi_bready,
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axi_arvalid,
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axi_arid,
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axi_arburst,
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axi_arlock,
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axi_arcache,
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axi_arprot,
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axi_arqos,
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axi_aruser,
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axi_arlen,
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axi_arsize,
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axi_araddr,
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axi_arready,
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axi_rvalid,
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axi_rid,
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axi_ruser,
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axi_rresp,
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axi_rlast,
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axi_rdata,
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axi_rready,
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// transfer request
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axi_xfer_req);
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// parameters
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parameter DATA_WIDTH = 32;
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parameter AXI_SIZE = 2;
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parameter AXI_LENGTH = 16;
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parameter AXI_ADDRESS = 32'h00000000;
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// fifo interface
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input m_rst;
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input m_clk;
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input m_wr;
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input [DATA_WIDTH-1:0] m_wdata;
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output m_wovf;
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output axi_mwr;
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output [DATA_WIDTH-1:0] axi_mwdata;
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input axi_mwovf;
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input axi_mwpfull;
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// axi interface
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input axi_clk;
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input axi_resetn;
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output axi_awvalid;
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output [ 3:0] axi_awid;
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output [ 1:0] axi_awburst;
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output axi_awlock;
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output [ 3:0] axi_awcache;
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output [ 2:0] axi_awprot;
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output [ 3:0] axi_awqos;
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output [ 3:0] axi_awuser;
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output [ 7:0] axi_awlen;
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output [ 2:0] axi_awsize;
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output [ 31:0] axi_awaddr;
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input axi_awready;
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output axi_wvalid;
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output [DATA_WIDTH-1:0] axi_wdata;
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output [(DATA_WIDTH/8)-1:0] axi_wstrb;
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output axi_wlast;
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output [ 3:0] axi_wuser;
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input axi_wready;
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input axi_bvalid;
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input [ 3:0] axi_bid;
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input [ 1:0] axi_bresp;
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input [ 3:0] axi_buser;
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output axi_bready;
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output axi_arvalid;
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output [ 3:0] axi_arid;
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output [ 1:0] axi_arburst;
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output axi_arlock;
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output [ 3:0] axi_arcache;
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output [ 2:0] axi_arprot;
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output [ 3:0] axi_arqos;
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output [ 3:0] axi_aruser;
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output [ 7:0] axi_arlen;
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output [ 2:0] axi_arsize;
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output [ 31:0] axi_araddr;
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input axi_arready;
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input axi_rvalid;
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input [ 3:0] axi_rid;
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input [ 3:0] axi_ruser;
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input [ 1:0] axi_rresp;
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input axi_rlast;
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input [DATA_WIDTH-1:0] axi_rdata;
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output axi_rready;
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// transfer request
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input axi_xfer_req;
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// internal signals
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wire axi_rd_req_s;
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wire [ 31:0] axi_rd_addr_s;
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wire axi_rd_status_s;
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// instantiations
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axi_fifo2s_wr #(
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.DATA_WIDTH (DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH),
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.AXI_ADDRESS (AXI_ADDRESS))
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i_wr (
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.axi_xfer_req (axi_xfer_req),
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.axi_rd_req (axi_rd_req_s),
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.axi_rd_addr (axi_rd_addr_s),
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.axi_rd_status (axi_rd_status_s),
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.m_rst (m_rst),
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.m_clk (m_clk),
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.m_wr (m_wr),
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.m_wdata (m_wdata),
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.m_wovf (m_wovf),
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.axi_clk (axi_clk),
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.axi_resetn (axi_resetn),
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.axi_awvalid (axi_awvalid),
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.axi_awid (axi_awid),
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.axi_awburst (axi_awburst),
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.axi_awlock (axi_awlock),
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.axi_awcache (axi_awcache),
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.axi_awprot (axi_awprot),
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.axi_awqos (axi_awqos),
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.axi_awuser (axi_awuser),
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.axi_awlen (axi_awlen),
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.axi_awsize (axi_awsize),
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.axi_awaddr (axi_awaddr),
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.axi_awready (axi_awready),
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.axi_wvalid (axi_wvalid),
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.axi_wdata (axi_wdata),
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.axi_wstrb (axi_wstrb),
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.axi_wlast (axi_wlast),
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.axi_wuser (axi_wuser),
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.axi_wready (axi_wready),
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.axi_bvalid (axi_bvalid),
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.axi_bid (axi_bid),
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.axi_bresp (axi_bresp),
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.axi_buser (axi_buser),
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.axi_bready (axi_bready));
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axi_fifo2s_rd #(
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.DATA_WIDTH (DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH))
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i_rd (
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.axi_xfer_req (axi_xfer_req),
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.axi_rd_req (axi_rd_req_s),
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.axi_rd_addr (axi_rd_addr_s),
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.axi_rd_status (axi_rd_status_s),
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.axi_clk (axi_clk),
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.axi_resetn (axi_resetn),
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.axi_arvalid (axi_arvalid),
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.axi_arid (axi_arid),
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.axi_arburst (axi_arburst),
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.axi_arlock (axi_arlock),
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.axi_arcache (axi_arcache),
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.axi_arprot (axi_arprot),
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.axi_arqos (axi_arqos),
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.axi_aruser (axi_aruser),
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.axi_arlen (axi_arlen),
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.axi_arsize (axi_arsize),
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.axi_araddr (axi_araddr),
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.axi_arready (axi_arready),
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.axi_rvalid (axi_rvalid),
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.axi_rid (axi_rid),
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.axi_ruser (axi_ruser),
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.axi_rresp (axi_rresp),
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.axi_rlast (axi_rlast),
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.axi_rdata (axi_rdata),
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.axi_rready (axi_rready),
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.axi_mwr (axi_mwr),
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.axi_mwdata (axi_mwdata),
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.axi_mwovf (axi_mwovf),
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.axi_mwpfull (axi_mwpfull));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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