61 lines
2.5 KiB
Tcl
61 lines
2.5 KiB
Tcl
# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_ad9963
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adi_ip_files axi_ad9963 [list \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
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"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
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"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
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"$ad_hdl_dir/library/common/ad_pnmon.v" \
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"$ad_hdl_dir/library/common/ad_dds_sine.v" \
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"$ad_hdl_dir/library/common/ad_dds_1.v" \
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"$ad_hdl_dir/library/common/ad_dds.v" \
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"$ad_hdl_dir/library/common/ad_datafmt.v" \
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"$ad_hdl_dir/library/common/ad_iqcor.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/up_dac_common.v" \
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"$ad_hdl_dir/library/common/up_dac_channel.v" \
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"axi_ad9963_constr.xdc" \
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"axi_ad9963_if.v" \
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"axi_ad9963_rx_pnmon.v" \
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"axi_ad9963_rx_channel.v" \
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"axi_ad9963_rx.v" \
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"axi_ad9963_tx_channel.v" \
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"axi_ad9963_tx.v" \
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"axi_ad9963.v" ]
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adi_ip_properties axi_ad9963
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set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
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adi_set_ports_dependency "delay_clk" \
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"(spirit:decode(id('MODELPARAM_VALUE.ADC_IODELAY_ENABLE')) = 1)" 0
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ipx::infer_bus_interface trx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::save_core [ipx::current_core]
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