143 lines
4.1 KiB
Verilog
143 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_gpreg_clock_mon #(
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parameter ID = 0,
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parameter BUF_ENABLE = 0) (
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// clock
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input d_clk,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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// internal registers
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reg up_d_preset = 'd0;
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reg up_d_resetn = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire [31:0] up_d_count_s;
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wire d_rst;
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wire d_clk_g;
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// decode block select
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assign up_wreq_s = (up_waddr[13:4] == ID) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:4] == ID) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_d_preset <= 1'd1;
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up_wack <= 'd0;
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up_d_resetn <= 'd0;
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end else begin
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up_d_preset <= ~up_d_resetn;
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_d_resetn <= up_wdata[0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[3:0])
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4'b0000: up_rdata <= {31'd0, up_d_resetn};
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4'b0010: up_rdata <= up_d_count_s;
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default: up_rdata <= 32'd0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// clock monitor
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up_clock_mon i_clock_mon (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_d_count (up_d_count_s),
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.d_rst (d_rst),
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.d_clk (d_clk_g));
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ad_rst i_d_rst_reg (
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.preset (up_d_preset),
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.clk (d_clk_g),
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.rst (d_rst));
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generate
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if (BUF_ENABLE == 1) begin
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BUFG i_bufg (
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.I (d_clk),
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.O (d_clk_g));
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end else begin
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assign d_clk_g = d_clk;
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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