3d5ef9a8ed
Due to the delay between the dac_valid and the fifo_valid signal we need to have two counters. One counter which counts the number of incoming dac_valid signals and generates the dma_rd signal and one counter for the offset which gets set to 0 when fifo_valid is set. This fixes issues with the unpack order when only one channel is active. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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util_dac_unpack.v | ||
util_dac_unpack_hw.tcl | ||
util_dac_unpack_ip.tcl |