6d4430cfda
When using non-broadcast access to the GT DRP registers lane filtering is done on both sides. The ready and data signals are filtered in the in the axi_adxcvr module and the enable signal is filtered in the util_adxcvr module. This works fine as long as both sides use the same transceiver IDs. E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the util_adxcvr module. But this is not always the case. E.g. on the ADRV9371 platform there are two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr. The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses lane 2 and 3. Non-broadcast access for the first RX axi_adxcvr module works fine, but always generates a timeout for the second axi_adxcvr module. This is because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the util_adxcvr and when ID based filtering is done both can't match at the same time. To avoid this perform the filtering for all the signals in the axi_adxcvr module. This makes sure that the same base ID is used. This also removes the sel signal from the transceiver interfaces since it is no longer used on the util_adxcvr side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| Makefile | ||
| axi_adxcvr.v | ||
| axi_adxcvr_es.v | ||
| axi_adxcvr_ip.tcl | ||
| axi_adxcvr_mdrp.v | ||
| axi_adxcvr_mstatus.v | ||
| axi_adxcvr_up.v | ||