211 lines
6.3 KiB
Verilog
211 lines
6.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ltc2387_channel #(
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parameter ADC_RES = 16,
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parameter OUT_RES = 16,
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parameter TWOLANES = 1,
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parameter USERPORTS_DISABLE = 0,
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parameter DATAFORMAT_DISABLE = 0
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) (
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// adc interface
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input adc_clk,
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input adc_rst,
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input adc_valid_in,
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input [ADC_RES-1:0] adc_data_in,
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// dma interface
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output adc_enable,
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output adc_valid,
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output [OUT_RES-1:0] adc_data,
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// error monitoring
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output up_adc_pn_err,
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output up_adc_pn_oos,
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output up_adc_or,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack
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);
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// internal signals
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wire adc_dfmt_valid_s;
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wire [15:0] adc_dfmt_data_s;
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wire adc_dcfilter_valid_s;
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wire adc_iqcor_enb_s;
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wire adc_dcfilt_enb_s;
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wire adc_dfmt_se_s;
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wire adc_dfmt_type_s;
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wire adc_dfmt_enable_s;
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wire [15:0] adc_dcfilt_offset_s;
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wire [15:0] adc_dcfilt_coeff_s;
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wire [15:0] adc_iqcor_coeff_1_s;
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wire [15:0] adc_iqcor_coeff_2_s;
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wire [ 3:0] adc_pnseq_sel_s;
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wire [ 3:0] adc_data_sel_s;
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reg adc_pn_err;
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wire adc_pn_err_s;
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wire [ADC_RES-1:0] test_pattern;
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wire [15:0] expected_pattern;
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assign adc_pn_err_s = adc_pn_err;
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// expected pattern
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generate
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if (TWOLANES == 1) begin
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assign expected_pattern = 16'b1100110000111111;
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end else begin
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assign expected_pattern = 16'b1010000001111111;
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end
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if (ADC_RES == 16) begin
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assign test_pattern = expected_pattern;
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end else if (ADC_RES == 18) begin
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assign test_pattern = expected_pattern << 2;
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end
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endgenerate
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always @(posedge adc_clk) begin
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if (test_pattern == adc_data) begin
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adc_pn_err <= 1'b0;
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end else begin
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adc_pn_err <= 1'b1;
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end
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end
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// min DMA bus width according to ADC_RES
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generate
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if (ADC_RES == 18) begin
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ad_datafmt #(
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.DATA_WIDTH (18),
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.BITS_PER_SAMPLE (32),
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.DISABLE (DATAFORMAT_DISABLE)
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) i_ad_datafmt (
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.clk (adc_clk),
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.valid (adc_valid_in),
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.data (adc_data_in),
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.valid_out (adc_valid),
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.data_out (adc_data),
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.dfmt_enable (adc_dfmt_enable_s),
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.dfmt_type (adc_dfmt_type_s),
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.dfmt_se (adc_dfmt_se_s));
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end else if (ADC_RES == 16) begin
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assign adc_data = adc_data_in;
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assign adc_valid = adc_valid_in;
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end else begin
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assign adc_data = 'd0;
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assign adc_valid = 1'd0;
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end
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endgenerate
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// adc channel regmap
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up_adc_channel #(
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.CHANNEL_ID (0),
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.USERPORTS_DISABLE (USERPORTS_DISABLE),
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.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
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.DCFILTER_DISABLE (1'b1),
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.IQCORRECTION_DISABLE (1'b1)
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) i_up_adc_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_enable (adc_enable),
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.adc_iqcor_enb (adc_iqcor_enb_s),
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.adc_dcfilt_enb (adc_dcfilt_enb_s),
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.adc_dfmt_se (adc_dfmt_se_s),
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.adc_dfmt_type (adc_dfmt_type_s),
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.adc_dfmt_enable (adc_dfmt_enable_s),
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.adc_dcfilt_offset (adc_dcfilt_offset_s),
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.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
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.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
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.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
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.adc_pnseq_sel (adc_pnseq_sel_s),
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.adc_data_sel (),
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.adc_pn_err (adc_pn_err_s),
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.adc_pn_oos (1'b0),
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.adc_or (1'b0),
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.adc_read_data ('d0),
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.adc_status_header ('d0),
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.adc_crc_err ('d0),
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.up_adc_pn_err (up_adc_pn_err),
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.up_adc_pn_oos (up_adc_pn_oos),
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.up_adc_or (up_adc_or),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd16),
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.adc_usr_datatype_bits (8'd16),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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