408 lines
12 KiB
Verilog
408 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module axi_dmac_transfer #(
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8),
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parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8),
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parameter DMA_TYPE_DEST = 0,
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parameter DMA_TYPE_SRC = 2,
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parameter DMA_AXI_ADDR_WIDTH = 32,
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parameter DMA_2D_TRANSFER = 1,
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parameter ASYNC_CLK_REQ_SRC = 1,
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parameter ASYNC_CLK_SRC_DEST = 1,
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parameter ASYNC_CLK_DEST_REQ = 1,
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parameter AXI_SLICE_DEST = 0,
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parameter AXI_SLICE_SRC = 0,
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parameter MAX_BYTES_PER_BURST = 128,
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parameter FIFO_SIZE = 8,
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parameter ID_WIDTH = $clog2(FIFO_SIZE*2),
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parameter AXI_LENGTH_WIDTH_SRC = 8,
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parameter AXI_LENGTH_WIDTH_DEST = 8
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) (
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input ctrl_clk,
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input ctrl_resetn,
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input ctrl_enable,
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input ctrl_pause,
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input req_valid,
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output req_ready,
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input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
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input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
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input [DMA_LENGTH_WIDTH-1:0] req_x_length,
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input [DMA_LENGTH_WIDTH-1:0] req_y_length,
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input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
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input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
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input req_sync_transfer_start,
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input req_last,
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output req_eot,
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// Master AXI interface
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input m_dest_axi_aclk,
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input m_dest_axi_aresetn,
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input m_src_axi_aclk,
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input m_src_axi_aresetn,
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// Write address
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output [DMA_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output [AXI_LENGTH_WIDTH_DEST-1:0] m_axi_awlen,
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output [2:0] m_axi_awsize,
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output [1:0] m_axi_awburst,
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output [2:0] m_axi_awprot,
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output [3:0] m_axi_awcache,
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output m_axi_awvalid,
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input m_axi_awready,
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// Write data
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output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata,
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output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb,
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input m_axi_wready,
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output m_axi_wvalid,
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output m_axi_wlast,
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// Write response
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input m_axi_bvalid,
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input [1:0] m_axi_bresp,
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output m_axi_bready,
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// Read address
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input m_axi_arready,
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output m_axi_arvalid,
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output [DMA_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output [AXI_LENGTH_WIDTH_SRC-1:0] m_axi_arlen,
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output [2:0] m_axi_arsize,
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output [1:0] m_axi_arburst,
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output [2:0] m_axi_arprot,
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output [3:0] m_axi_arcache,
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// Read data and response
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input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata,
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output m_axi_rready,
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input m_axi_rvalid,
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input [1:0] m_axi_rresp,
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// Slave streaming AXI interface
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input s_axis_aclk,
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output s_axis_ready,
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input s_axis_valid,
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input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
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input [0:0] s_axis_user,
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input s_axis_last,
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output s_axis_xfer_req,
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// Master streaming AXI interface
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input m_axis_aclk,
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input m_axis_ready,
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output m_axis_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
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output m_axis_last,
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output m_axis_xfer_req,
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// Input FIFO interface
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input fifo_wr_clk,
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input fifo_wr_en,
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input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
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output fifo_wr_overflow,
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input fifo_wr_sync,
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output fifo_wr_xfer_req,
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// Input FIFO interface
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input fifo_rd_clk,
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input fifo_rd_en,
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output fifo_rd_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
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output fifo_rd_underflow,
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output fifo_rd_xfer_req,
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output [ID_WIDTH-1:0] dbg_dest_request_id,
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output [ID_WIDTH-1:0] dbg_dest_address_id,
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output [ID_WIDTH-1:0] dbg_dest_data_id,
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output [ID_WIDTH-1:0] dbg_dest_response_id,
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output [ID_WIDTH-1:0] dbg_src_request_id,
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output [ID_WIDTH-1:0] dbg_src_address_id,
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output [ID_WIDTH-1:0] dbg_src_data_id,
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output [ID_WIDTH-1:0] dbg_src_response_id,
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output [11:0] dbg_status
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);
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wire dma_req_valid;
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wire dma_req_ready;
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wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
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wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
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wire [DMA_LENGTH_WIDTH-1:0] dma_req_length;
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wire dma_req_eot;
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wire dma_req_sync_transfer_start;
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wire dma_req_last;
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wire req_clk = ctrl_clk;
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wire req_resetn;
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wire req_enable;
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wire dest_clk;
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wire dest_ext_resetn;
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wire dest_resetn;
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wire dest_enable;
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wire dest_enabled;
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wire src_clk;
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wire src_ext_resetn;
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wire src_resetn;
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wire src_enable;
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wire src_enabled;
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wire req_valid_gated;
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wire req_ready_gated;
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axi_dmac_reset_manager #(
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.ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC),
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.ASYNC_CLK_SRC_DEST (ASYNC_CLK_SRC_DEST),
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.ASYNC_CLK_DEST_REQ (ASYNC_CLK_DEST_REQ)
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) i_reset_manager (
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.clk (ctrl_clk),
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.resetn (ctrl_resetn),
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.ctrl_enable (ctrl_enable),
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.ctrl_pause (ctrl_pause),
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.req_resetn (req_resetn),
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.req_enable (req_enable),
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.req_enabled (req_enable),
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.dest_clk (dest_clk),
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.dest_ext_resetn (dest_ext_resetn),
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.dest_resetn (dest_resetn),
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.dest_enable (dest_enable),
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.dest_enabled (dest_enabled),
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.src_clk (src_clk),
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.src_ext_resetn (src_ext_resetn),
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.src_resetn (src_resetn),
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.src_enable (src_enable),
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.src_enabled (src_enabled),
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.dbg_status (dbg_status)
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);
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/*
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* Things become a lot easier if we gate incoming requests in a central place
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* before they are propagated downstream. Otherwise we'd need to take special
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* care to not accidentally accept requests while the DMA is going through a
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* shutdown and reset phase.
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*/
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assign req_valid_gated = req_enable & req_valid;
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assign req_ready = req_enable & req_ready_gated;
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generate if (DMA_2D_TRANSFER == 1) begin
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dmac_2d_transfer #(
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.DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH),
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.BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST),
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.BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC)
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) i_2d_transfer (
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.req_aclk (req_clk),
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.req_aresetn (req_resetn),
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.req_eot (req_eot),
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.req_valid (req_valid_gated),
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.req_ready (req_ready_gated),
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.req_dest_address (req_dest_address),
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.req_src_address (req_src_address),
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.req_x_length (req_x_length),
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.req_y_length (req_y_length),
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.req_dest_stride (req_dest_stride),
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.req_src_stride (req_src_stride),
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.req_sync_transfer_start (req_sync_transfer_start),
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.out_req_valid (dma_req_valid),
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.out_req_ready (dma_req_ready),
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.out_req_dest_address (dma_req_dest_address),
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.out_req_src_address (dma_req_src_address),
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.out_req_length (dma_req_length),
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.out_req_sync_transfer_start (dma_req_sync_transfer_start),
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.out_eot (dma_req_eot)
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);
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assign dma_req_last = 1'b0;
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end else begin
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/* Request */
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assign dma_req_valid = req_valid_gated;
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assign req_ready_gated = dma_req_ready;
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assign dma_req_dest_address = req_dest_address;
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assign dma_req_src_address = req_src_address;
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assign dma_req_length = req_x_length;
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assign dma_req_sync_transfer_start = req_sync_transfer_start;
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assign dma_req_last = req_last;
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/* Response */
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assign req_eot = dma_req_eot;
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end endgenerate
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dmac_request_arb #(
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.DMA_DATA_WIDTH_SRC (DMA_DATA_WIDTH_SRC),
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.DMA_DATA_WIDTH_DEST (DMA_DATA_WIDTH_DEST),
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.DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH),
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.BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST),
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.BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC),
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.DMA_TYPE_DEST (DMA_TYPE_DEST),
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.DMA_TYPE_SRC (DMA_TYPE_SRC),
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.DMA_AXI_ADDR_WIDTH (DMA_AXI_ADDR_WIDTH),
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.ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC),
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.ASYNC_CLK_SRC_DEST (ASYNC_CLK_SRC_DEST),
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.ASYNC_CLK_DEST_REQ (ASYNC_CLK_DEST_REQ),
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.AXI_SLICE_DEST (AXI_SLICE_DEST),
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.AXI_SLICE_SRC (AXI_SLICE_SRC),
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.MAX_BYTES_PER_BURST (MAX_BYTES_PER_BURST),
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.FIFO_SIZE (FIFO_SIZE),
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.ID_WIDTH (ID_WIDTH),
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.AXI_LENGTH_WIDTH_DEST (AXI_LENGTH_WIDTH_DEST),
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.AXI_LENGTH_WIDTH_SRC (AXI_LENGTH_WIDTH_SRC)
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) i_request_arb (
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.req_clk (req_clk),
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.req_resetn (req_resetn),
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.req_valid (dma_req_valid),
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.req_ready (dma_req_ready),
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.req_dest_address (dma_req_dest_address),
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.req_src_address (dma_req_src_address),
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.req_length (dma_req_length),
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.req_xlast (dma_req_last),
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.req_sync_transfer_start (dma_req_sync_transfer_start),
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.eot (dma_req_eot),
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.req_enable (req_enable),
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.dest_clk (dest_clk),
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.dest_ext_resetn (dest_ext_resetn),
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.dest_resetn (dest_resetn),
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.dest_enable (dest_enable),
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.dest_enabled (dest_enabled),
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.src_clk (src_clk),
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.src_ext_resetn (src_ext_resetn),
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.src_resetn (src_resetn),
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.src_enable (src_enable),
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.src_enabled (src_enabled),
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.m_dest_axi_aclk (m_dest_axi_aclk),
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.m_dest_axi_aresetn (m_dest_axi_aresetn),
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.m_src_axi_aclk (m_src_axi_aclk),
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.m_src_axi_aresetn (m_src_axi_aresetn),
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.m_axi_awvalid (m_axi_awvalid),
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.m_axi_awready (m_axi_awready),
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.m_axi_awaddr (m_axi_awaddr),
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.m_axi_awlen (m_axi_awlen),
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.m_axi_awsize (m_axi_awsize),
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.m_axi_awburst (m_axi_awburst),
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.m_axi_awprot (m_axi_awprot),
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.m_axi_awcache (m_axi_awcache),
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.m_axi_wvalid (m_axi_wvalid),
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.m_axi_wready (m_axi_wready),
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.m_axi_wdata (m_axi_wdata),
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.m_axi_wstrb (m_axi_wstrb),
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.m_axi_wlast (m_axi_wlast),
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.m_axi_bvalid (m_axi_bvalid),
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.m_axi_bready (m_axi_bready),
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.m_axi_bresp (m_axi_bresp),
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.m_axi_arvalid (m_axi_arvalid),
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.m_axi_arready (m_axi_arready),
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.m_axi_araddr (m_axi_araddr),
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.m_axi_arlen (m_axi_arlen),
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.m_axi_arsize (m_axi_arsize),
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.m_axi_arburst (m_axi_arburst),
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.m_axi_arprot (m_axi_arprot),
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.m_axi_arcache (m_axi_arcache),
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.m_axi_rready (m_axi_rready),
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.m_axi_rvalid (m_axi_rvalid),
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.m_axi_rdata (m_axi_rdata),
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.m_axi_rresp (m_axi_rresp),
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.s_axis_aclk (s_axis_aclk),
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.s_axis_ready (s_axis_ready),
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.s_axis_valid (s_axis_valid),
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.s_axis_data (s_axis_data),
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.s_axis_user (s_axis_user),
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.s_axis_last (s_axis_last),
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.s_axis_xfer_req (s_axis_xfer_req),
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.m_axis_aclk (m_axis_aclk),
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.m_axis_ready (m_axis_ready),
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.m_axis_valid (m_axis_valid),
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.m_axis_data (m_axis_data),
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.m_axis_last (m_axis_last),
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.m_axis_xfer_req (m_axis_xfer_req),
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.fifo_wr_clk (fifo_wr_clk),
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.fifo_wr_en (fifo_wr_en),
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.fifo_wr_din (fifo_wr_din),
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.fifo_wr_overflow (fifo_wr_overflow),
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.fifo_wr_sync (fifo_wr_sync),
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.fifo_wr_xfer_req (fifo_wr_xfer_req),
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.fifo_rd_clk (fifo_rd_clk),
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.fifo_rd_en (fifo_rd_en),
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.fifo_rd_valid (fifo_rd_valid),
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.fifo_rd_dout (fifo_rd_dout),
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.fifo_rd_underflow (fifo_rd_underflow),
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.fifo_rd_xfer_req (fifo_rd_xfer_req),
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.dbg_dest_request_id (dbg_dest_request_id),
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.dbg_dest_address_id (dbg_dest_address_id),
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.dbg_dest_data_id (dbg_dest_data_id),
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.dbg_dest_response_id (dbg_dest_response_id),
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.dbg_src_request_id (dbg_src_request_id),
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.dbg_src_address_id (dbg_src_address_id),
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.dbg_src_data_id (dbg_src_data_id),
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.dbg_src_response_id (dbg_src_response_id)
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);
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endmodule
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