138 lines
4.0 KiB
Verilog
138 lines
4.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_dac#(
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parameter CHANNEL_ID = 0,
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parameter DATA_WIDTH = 16) (
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input clk,
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// control ports
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input [31:0] control,
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output reg [31:0] status,
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// FIFO interface
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output reg src_dac_enable,
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input [(DATA_WIDTH-1):0] src_dac_data,
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output reg src_dac_valid,
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input dst_dac_enable,
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output reg [(DATA_WIDTH-1):0] dst_dac_data,
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input dst_dac_valid);
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localparam SYMBOL_WIDTH = 2;
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localparam RP_ID = 8'hA2;
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// output register to improve timing
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// internal registers
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reg [ 7:0] pn_data = 'hF2;
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reg [ 3:0] mode = 'h0;
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// internal wires
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wire [(SYMBOL_WIDTH-1):0] mod_data;
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wire [15:0] dac_data_fltr_i;
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wire [15:0] dac_data_fltr_q;
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// prbs function
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function [ 7:0] pn;
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input [ 7:0] din;
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reg [ 7:0] dout;
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begin
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dout[7] = din[6];
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dout[6] = din[5];
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dout[5] = din[4];
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dout[4] = din[3];
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dout[3] = din[2];
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dout[2] = din[1];
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dout[1] = din[7] ^ din[4];
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dout[0] = din[6] ^ din[3];
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pn = dout;
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end
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endfunction
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// update control and status registers
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always @(posedge clk) begin
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status <= { 24'h0, RP_ID };
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mode <= control[ 7:4];
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end
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// prbs generation
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always @(posedge clk) begin
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if((dst_dac_en == 1) && (dst_dac_enable == 1)) begin
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pn_data <= pn(pn_data);
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end
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end
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// data for the modulator (prbs or dma)
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assign mod_data = (mode == 1) ? pn_data[ 1:0] : src_dac_data[ 1:0];
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// qpsk modulator
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qpsk_mod i_qpsk_mod (
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.clk(clk),
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.data_input(mod_data),
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.data_valid(dst_dac_en),
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.data_qpsk_i(dac_data_fltr_i),
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.data_qpsk_q(dac_data_fltr_q)
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);
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// output logic
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always @(posedge clk) begin
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src_dac_enable <= dst_dac_en;
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src_dac_valid <= dst_dac_valid;
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case(mode)
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4'h0 : begin
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dst_dac_data <= src_dac_data;
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end
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4'h1 : begin
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dst_dac_data <= { dac_data_fltr_q, dac_data_fltr_i };
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end
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4'h2 : begin
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dst_dac_data <= { dac_data_fltr_q, dac_data_fltr_i };
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end
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default : begin
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end
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endcase
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end
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endmodule
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