8fdd27c605
By default inferred output reset signals have an active low polarity. The axi_ad9361 rst output signal is active high though. Currently when connecting it to a input reset with active high polarity will generate an error in IPI. Fix this by explicitly marking the polarity of the rst signal as active high. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| altera | ||
| xilinx | ||
| Makefile | ||
| axi_ad9361.v | ||
| axi_ad9361_constr.sdc | ||
| axi_ad9361_constr.xdc | ||
| axi_ad9361_delay.tcl | ||
| axi_ad9361_hw.tcl | ||
| axi_ad9361_ip.tcl | ||
| axi_ad9361_rx.v | ||
| axi_ad9361_rx_channel.v | ||
| axi_ad9361_rx_pnmon.v | ||
| axi_ad9361_tdd.v | ||
| axi_ad9361_tdd_if.v | ||
| axi_ad9361_tx.v | ||
| axi_ad9361_tx_channel.v | ||