109 lines
3.5 KiB
Verilog
109 lines
3.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// data format (offset binary or 2's complement only)
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`timescale 1ps/1ps
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module ad_datafmt #(
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// data bus width
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parameter DATA_WIDTH = 16,
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parameter DISABLE = 0) (
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// data path
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input clk,
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input valid,
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input [(DATA_WIDTH-1):0] data,
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output valid_out,
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output [15:0] data_out,
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// control signals
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input dfmt_enable,
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input dfmt_type,
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input dfmt_se);
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// internal registers
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reg valid_int = 'd0;
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reg [15:0] data_int = 'd0;
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// internal signals
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wire type_s;
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wire [15:0] data_out_s;
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// data-path disable
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generate
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if (DISABLE == 1) begin
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assign valid_out = valid;
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assign data_out = data;
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end else begin
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assign valid_out = valid_int;
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assign data_out = data_int;
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end
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endgenerate
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// if offset-binary convert to 2's complement first
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assign type_s = dfmt_enable & dfmt_type;
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generate
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if (DATA_WIDTH < 16) begin
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wire signext_s;
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wire sign_s;
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assign signext_s = dfmt_enable & dfmt_se;
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assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
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assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
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end
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endgenerate
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assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)];
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assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0];
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always @(posedge clk) begin
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valid_int <= valid;
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data_int <= data_out_s[15:0];
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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