99 lines
4.1 KiB
Verilog
99 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// + A simple AXI stream data upscale module, which can be used with devices
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// with resolution which can not be aligned to a WORD (32 bits). Eg. 24 bits
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// + It has the same control interface as the ad_datafmt module, which controls
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// the data format inside a generic AXI converter core.
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// + Supports multiple channels. Contains a single register stage.
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`timescale 1ns/100ps
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module util_axis_upscale #(
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parameter NUM_OF_CHANNELS = 4,
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parameter DATA_WIDTH = 24,
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parameter UDATA_WIDTH = 32
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) (
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input clk,
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input resetn,
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input s_axis_valid,
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output reg s_axis_ready,
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input [(NUM_OF_CHANNELS*DATA_WIDTH)-1:0] s_axis_data,
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output reg m_axis_valid,
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input m_axis_ready,
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output reg [(NUM_OF_CHANNELS*UDATA_WIDTH)-1:0] m_axis_data,
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input dfmt_enable,
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input dfmt_type,
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input dfmt_se
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);
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wire type_s;
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wire signext_s;
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wire [(NUM_OF_CHANNELS*UDATA_WIDTH)-1:0] data_out_s;
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localparam MSB_WIDTH = UDATA_WIDTH - DATA_WIDTH;
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assign type_s = dfmt_enable & dfmt_type;
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assign signext_s = dfmt_enable & dfmt_se;
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genvar i;
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generate
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for (i=1; i <= NUM_OF_CHANNELS; i=i+1) begin : signext_data
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wire sign_s;
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assign sign_s = signext_s & (type_s ^ s_axis_data[(i*DATA_WIDTH-1)]);
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assign data_out_s[(i*UDATA_WIDTH-1):(i*UDATA_WIDTH-MSB_WIDTH)] = {(MSB_WIDTH){sign_s}};
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assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-1)] = type_s ^ s_axis_data[(i*DATA_WIDTH-1)];
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assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-2):((i-1)*UDATA_WIDTH)] = s_axis_data[(i*DATA_WIDTH-2):((i-1)*DATA_WIDTH)];
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end
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endgenerate
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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m_axis_valid <= 1'b0;
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s_axis_ready <= 1'b0;
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m_axis_data <= {(NUM_OF_CHANNELS*UDATA_WIDTH){1'b0}};
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end else begin
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m_axis_valid <= s_axis_valid;
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s_axis_ready <= m_axis_ready;
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m_axis_data <= data_out_s;
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end
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end
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endmodule
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