313 lines
9.8 KiB
Verilog
313 lines
9.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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inout iic_scl,
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inout iic_sda,
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output spi_clk,
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output spi_dio,
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input spi_do,
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output spi_en,
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// Device clock
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input fpga_ref_clk_n,
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input fpga_ref_clk_p,
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// Device clock passed through 9001
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input dev_clk_in,
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input fpga_mcs_in_n,
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input fpga_mcs_in_p,
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output dev_mcs_fpga_out_n,
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output dev_mcs_fpga_out_p,
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inout dgpio_0,
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inout dgpio_1,
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inout dgpio_2,
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inout dgpio_3,
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inout dgpio_4,
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inout dgpio_5,
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inout dgpio_6,
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inout dgpio_7,
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inout dgpio_8,
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inout dgpio_9,
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inout dgpio_10,
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inout dgpio_11,
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inout gp_int,
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inout mode,
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inout reset_trx,
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input rx1_dclk_in_n,
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input rx1_dclk_in_p,
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output rx1_enable,
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input rx1_idata_in_n,
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input rx1_idata_in_p,
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input rx1_qdata_in_n,
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input rx1_qdata_in_p,
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input rx1_strobe_in_n,
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input rx1_strobe_in_p,
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input rx2_dclk_in_n,
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input rx2_dclk_in_p,
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output rx2_enable,
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input rx2_idata_in_n,
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input rx2_idata_in_p,
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input rx2_qdata_in_n,
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input rx2_qdata_in_p,
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input rx2_strobe_in_n,
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input rx2_strobe_in_p,
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output tx1_dclk_out_n,
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output tx1_dclk_out_p,
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input tx1_dclk_in_n,
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input tx1_dclk_in_p,
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output tx1_enable,
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output tx1_idata_out_n,
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output tx1_idata_out_p,
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output tx1_qdata_out_n,
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output tx1_qdata_out_p,
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output tx1_strobe_out_n,
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output tx1_strobe_out_p,
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output tx2_dclk_out_n,
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output tx2_dclk_out_p,
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input tx2_dclk_in_n,
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input tx2_dclk_in_p,
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output tx2_enable,
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output tx2_idata_out_n,
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output tx2_idata_out_p,
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output tx2_qdata_out_n,
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output tx2_qdata_out_p,
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output tx2_strobe_out_n,
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output tx2_strobe_out_p,
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inout sm_fan_tach,
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input vadj_err,
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output platform_status,
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inout tdd_sync,
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//debug hdr
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output [9:0] proto_hdr
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);
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// internal registers
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reg [ 2:0] mcs_sync_m = 'd0;
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reg dev_mcs_fpga_in = 1'b0;
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [94:0] gpio_t;
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wire gpio_rx1_enable_in;
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wire gpio_rx2_enable_in;
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wire gpio_tx1_enable_in;
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wire gpio_tx2_enable_in;
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wire [ 2:0] spi_csn;
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wire fpga_ref_clk;
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wire fpga_mcs_in;
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wire tdd_sync_loc;
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wire tdd_sync_i;
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wire tdd_sync_cntr;
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// instantiations
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IBUFDS i_ibufgs_fpga_ref_clk (
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.I (fpga_ref_clk_p),
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.IB (fpga_ref_clk_n),
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.O (fpga_ref_clk));
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IBUFDS i_ibufgs_fpga_mcs_in (
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.I (fpga_mcs_in_p),
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.IB (fpga_mcs_in_n),
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.O (fpga_mcs_in));
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OBUFDS i_obufds_dev_mcs_fpga_in (
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.I (dev_mcs_fpga_in),
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.O (dev_mcs_fpga_out_p),
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.OB (dev_mcs_fpga_out_n));
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// multi-chip synchronization
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//
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always @(posedge fpga_ref_clk) begin
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mcs_sync_m <= {mcs_sync_m[1:0], gpio_o[53]};
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dev_mcs_fpga_in <= mcs_sync_m[2] & ~mcs_sync_m[1];
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end
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// multi-ssi synchronization
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//
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assign mssi_sync = gpio_o[54];
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assign platform_status = vadj_err;
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ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
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.dio_t ({gpio_t[47:32]}),
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.dio_i ({gpio_o[47:32]}),
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.dio_o ({gpio_i[47:32]}),
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.dio_p ({sm_fan_tach, // 47
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reset_trx, // 46
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mode, // 45
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gp_int, // 44
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dgpio_11, // 43
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dgpio_10, // 42
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dgpio_9, // 41
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dgpio_8, // 40
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dgpio_7, // 39
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dgpio_6, // 38
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dgpio_5, // 37
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dgpio_4, // 36
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dgpio_3, // 35
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dgpio_2, // 34
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dgpio_1, // 33
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dgpio_0 })); // 32
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assign gpio_rx1_enable_in = gpio_o[48];
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assign gpio_rx2_enable_in = gpio_o[49];
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assign gpio_tx1_enable_in = gpio_o[50];
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assign gpio_tx2_enable_in = gpio_o[51];
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assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
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assign gpio_i[20: 8] = gpio_bd_i;
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assign gpio_bd_o = gpio_o[ 7: 0];
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assign gpio_i[54:48] = gpio_o[54:48];
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assign gpio_i[55] = vadj_err;
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assign gpio_i[94:56] = gpio_o[94:56];
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assign gpio_i[31:21] = gpio_o[31:21];
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assign spi_en = spi_csn[0];
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assign tdd_sync_loc = gpio_o[56];
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// tdd_sync_loc - local sync signal from a GPIO or other source
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// tdd_sync - external sync
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assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync;
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assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz;
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system_wrapper i_system_wrapper (
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.ref_clk (fpga_ref_clk),
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.mssi_sync (mssi_sync),
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.tx_output_enable (1'b1),
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.rx1_dclk_in_n (rx1_dclk_in_n),
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.rx1_dclk_in_p (rx1_dclk_in_p),
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.rx1_idata_in_n (rx1_idata_in_n),
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.rx1_idata_in_p (rx1_idata_in_p),
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.rx1_qdata_in_n (rx1_qdata_in_n),
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.rx1_qdata_in_p (rx1_qdata_in_p),
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.rx1_strobe_in_n (rx1_strobe_in_n),
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.rx1_strobe_in_p (rx1_strobe_in_p),
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.rx2_dclk_in_n (rx2_dclk_in_n),
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.rx2_dclk_in_p (rx2_dclk_in_p),
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.rx2_idata_in_n (rx2_idata_in_n),
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.rx2_idata_in_p (rx2_idata_in_p),
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.rx2_qdata_in_n (rx2_qdata_in_n),
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.rx2_qdata_in_p (rx2_qdata_in_p),
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.rx2_strobe_in_n (rx2_strobe_in_n),
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.rx2_strobe_in_p (rx2_strobe_in_p),
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.tx1_dclk_out_n (tx1_dclk_out_n),
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.tx1_dclk_out_p (tx1_dclk_out_p),
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.tx1_dclk_in_n (tx1_dclk_in_n),
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.tx1_dclk_in_p (tx1_dclk_in_p),
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.tx1_idata_out_n (tx1_idata_out_n),
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.tx1_idata_out_p (tx1_idata_out_p),
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.tx1_qdata_out_n (tx1_qdata_out_n),
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.tx1_qdata_out_p (tx1_qdata_out_p),
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.tx1_strobe_out_n (tx1_strobe_out_n),
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.tx1_strobe_out_p (tx1_strobe_out_p),
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.tx2_dclk_out_n (tx2_dclk_out_n),
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.tx2_dclk_out_p (tx2_dclk_out_p),
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.tx2_dclk_in_n (tx2_dclk_in_n),
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.tx2_dclk_in_p (tx2_dclk_in_p),
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.tx2_idata_out_n (tx2_idata_out_n),
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.tx2_idata_out_p (tx2_idata_out_p),
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.tx2_qdata_out_n (tx2_qdata_out_n),
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.tx2_qdata_out_p (tx2_qdata_out_p),
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.tx2_strobe_out_n (tx2_strobe_out_n),
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.tx2_strobe_out_p (tx2_strobe_out_p),
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.rx1_enable (rx1_enable),
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.rx2_enable (rx2_enable),
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.tx1_enable (tx1_enable),
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.tx2_enable (tx2_enable),
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.gpio_rx1_enable_in (gpio_rx1_enable_in),
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.gpio_rx2_enable_in (gpio_rx2_enable_in),
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.gpio_tx1_enable_in (gpio_tx1_enable_in),
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.gpio_tx2_enable_in (gpio_tx2_enable_in),
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.tdd_sync (tdd_sync_i),
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.tdd_sync_cntr (tdd_sync_cntr),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.spi0_sclk (spi_clk),
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.spi0_csn (spi_csn),
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.spi0_miso (spi_do),
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.spi0_mosi (spi_dio),
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.spi1_sclk (),
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.spi1_csn (),
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.spi1_miso (1'b0),
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.spi1_mosi (),
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// debug
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.adc1_div_clk (proto_hdr[0]),
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.adc2_div_clk (proto_hdr[1]),
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.dac1_div_clk (proto_hdr[2]),
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.dac2_div_clk (proto_hdr[3])
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);
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assign proto_hdr[9:4] = {'b0};
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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