144 lines
5.0 KiB
Verilog
144 lines
5.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad6676 #(
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parameter ID = 0,
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parameter NUM_LANES = 2,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0) (
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk,
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input [ 3:0] rx_sof,
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input rx_valid,
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output rx_ready,
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input [32*NUM_LANES-1:0] rx_data,
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// dma interface
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output adc_clk,
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output adc_valid_0,
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output adc_enable_0,
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output [31:0] adc_data_0,
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output adc_valid_1,
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output adc_enable_1,
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output [31:0] adc_data_1,
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input adc_dovf,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [11:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [11:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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assign adc_clk = rx_clk;
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ad_ip_jesd204_tpl_adc #(
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.ID (ID),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.NUM_LANES (NUM_LANES),
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.NUM_CHANNELS (2),
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.SAMPLES_PER_FRAME (1),
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.CONVERTER_RESOLUTION (16),
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.BITS_PER_SAMPLE (16),
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.OCTETS_PER_BEAT (4),
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.TWOS_COMPLEMENT (0)
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) i_adc_jesd204 (
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.link_clk (rx_clk),
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.link_sof (rx_sof),
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.link_valid (rx_valid),
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.link_data (rx_data),
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.link_ready (rx_ready),
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.enable ({adc_enable_1,adc_enable_0}),
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.adc_valid ({adc_valid_1,adc_valid_0}),
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.adc_data ({adc_data_1,adc_data_0}),
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.adc_dovf (adc_dovf),
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awready (s_axi_awready),
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awprot (s_axi_awprot),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wready (s_axi_wready),
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bready (s_axi_bready),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_arready (s_axi_arready),
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arprot (s_axi_arprot),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready(s_axi_rready),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rdata (s_axi_rdata)
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);
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endmodule
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