Maxim 341221dc91 jesd204: Update jesd204_tx_lane.v ... Removed decoder for tx_ready.		2020-04-01 10:29:40 +03:00
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Makefile	jesd204_tx: Support for 64b mode in transmit peripheral	2020-02-10 09:47:07 +02:00
jesd204_tx.v	jesd204_tx: Support for 64b mode in transmit peripheral	2020-02-10 09:47:07 +02:00
jesd204_tx_constr.sdc	jesd204: Add Altera/Intel IP support	2017-08-21 11:09:42 +02:00
jesd204_tx_constr.ttcl	jesd204_rx/tx: make SYSREF IOB placement optional	2018-07-24 09:16:24 +03:00
jesd204_tx_ctrl.v	sync_bits: Change I/O names of wires "in" and "out" for VHDL users	2019-04-23 18:03:23 +03:00
jesd204_tx_header.v	jesd204_tx: Support for 64b mode in transmit peripheral	2020-02-10 09:47:07 +02:00
jesd204_tx_hw.tcl	jesd204_tx: add output pipeline stage	2020-02-07 09:02:46 +02:00
jesd204_tx_ip.tcl	jesd204_tx: Support for 64b mode in transmit peripheral	2020-02-10 09:47:07 +02:00
jesd204_tx_lane.v	jesd204: Update jesd204_tx_lane.v	2020-04-01 10:29:40 +03:00
jesd204_tx_lane_64b.v	jesd204_tx: Support for 64b mode in transmit peripheral	2020-02-10 09:47:07 +02:00