106 lines
3.7 KiB
Verilog
106 lines
3.7 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module crc12_tb;
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parameter VCD_FILE = "crc12_tb.vcd";
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`define TIMEOUT 400
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`include "tb_base.v"
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reg [63:0] data_in = 'h0;
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reg [11:0] ref_crc12 = 'h0;
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wire [11:0] crc12;
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reg test_en = 1'b1;
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reg init = 1'b0;
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jesd204_crc12 DUT (
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.clk (clk),
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.reset (1'b0),
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.init (init),
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.data_in (data_in),
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.crc12 (crc12)
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);
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// Test against dataset from the standard
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// - Test contiguous input stream with init phase
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initial begin
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@(negedge reset);
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@(posedge clk);
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repeat (3) begin
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@(posedge clk) data_in <= 'h80_01_02_03_05_05_04_23;
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init <= 1'b1;
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@(posedge clk) data_in <= 'h0e_43_80_c2_0b_50_81_cd;
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init <= 1'b0;
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@(posedge clk) data_in <= 'h04_e7_83_92_5a_3c_aa_51;
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@(posedge clk) data_in <= 'h05_4d_87_d9_31_3d_11_51;
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end
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@(posedge clk);
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@(posedge clk);
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test_en <= 1'b0;
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end
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initial begin
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@(negedge reset);
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@(posedge clk);
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@(posedge clk);
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repeat(3) begin
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@(posedge clk) ref_crc12 <= 'hd00;
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@(posedge clk) ref_crc12 <= 'h11c;
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@(posedge clk) ref_crc12 <= 'hfea;
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@(posedge clk) ref_crc12 <= 'h5fe;
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end
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end
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always @(posedge clk) begin
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if (ref_crc12 != crc12 && failed == 1'b0 && test_en) begin
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failed <= 1'b1;
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end
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end
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endmodule
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