276 lines
10 KiB
Verilog
276 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_mfifo #(
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parameter NUM_OF_CHANNELS = 4,
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parameter DIN_DATA_WIDTH = 32,
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parameter ADDRESS_WIDTH = 8) (
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// d-in interface
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input din_rst,
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input din_clk,
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input din_valid,
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input [DIN_DATA_WIDTH-1:0] din_data_0,
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input [DIN_DATA_WIDTH-1:0] din_data_1,
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input [DIN_DATA_WIDTH-1:0] din_data_2,
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input [DIN_DATA_WIDTH-1:0] din_data_3,
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input [DIN_DATA_WIDTH-1:0] din_data_4,
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input [DIN_DATA_WIDTH-1:0] din_data_5,
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input [DIN_DATA_WIDTH-1:0] din_data_6,
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input [DIN_DATA_WIDTH-1:0] din_data_7,
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// d-out interface
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input dout_rst,
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input dout_clk,
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output reg dout_valid,
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output [15:0] dout_data_0,
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output [15:0] dout_data_1,
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output [15:0] dout_data_2,
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output [15:0] dout_data_3,
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output [15:0] dout_data_4,
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output [15:0] dout_data_5,
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output [15:0] dout_data_6,
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output [15:0] dout_data_7);
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// internal registers
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reg din_dout_toggle_m1 = 'd0;
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reg din_dout_toggle_m2 = 'd0;
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reg din_dout_toggle_m3 = 'd0;
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reg din_wr = 'd0;
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reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0;
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reg din_enable = 'd0;
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reg din_toggle = 'd0;
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reg dout_din_toggle_m1 = 'd0;
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reg dout_din_toggle_m2 = 'd0;
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reg dout_din_toggle_m3 = 'd0;
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reg [ 4:0] dout_cnt = 'd0;
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reg dout_ld = 'd0;
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reg dout_ld_d = 'd0;
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reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0;
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reg dout_enable = 'd0;
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reg dout_toggle = 'd0;
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reg [(DIN_DATA_WIDTH-1):0] dout_rdata_0 = 'd0;
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reg [(DIN_DATA_WIDTH-1):0] dout_rdata_1 = 'd0;
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reg [(DIN_DATA_WIDTH-1):0] dout_rdata_2 = 'd0;
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reg [(DIN_DATA_WIDTH-1):0] dout_rdata_3 = 'd0;
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reg [(DIN_DATA_WIDTH-1):0] dout_rdata_4 = 'd0;
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reg [(DIN_DATA_WIDTH-1):0] dout_rdata_5 = 'd0;
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reg [(DIN_DATA_WIDTH-1):0] dout_rdata_6 = 'd0;
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reg [(DIN_DATA_WIDTH-1):0] dout_rdata_7 = 'd0;
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// internal signals
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wire [(DIN_DATA_WIDTH-1):0] din_wdata_s[0:7];
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wire din_waddr_max_s;
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wire din_dout_toggle_s;
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wire dout_raddr_max_s;
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wire dout_rd_s;
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wire dout_din_toggle_s;
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wire [(DIN_DATA_WIDTH-1):0] dout_rdata_s[0:7];
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// variables
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genvar n;
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// write interface
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assign din_wdata_s[7] = din_data_7;
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assign din_wdata_s[6] = din_data_6;
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assign din_wdata_s[5] = din_data_5;
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assign din_wdata_s[4] = din_data_4;
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assign din_wdata_s[3] = din_data_3;
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assign din_wdata_s[2] = din_data_2;
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assign din_wdata_s[1] = din_data_1;
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assign din_wdata_s[0] = din_data_0;
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assign din_waddr_max_s = & din_waddr;
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assign din_dout_toggle_s = din_dout_toggle_m3 ^ din_dout_toggle_m2;
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always @(posedge din_clk or posedge din_rst) begin
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if (din_rst == 1'b1) begin
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din_dout_toggle_m1 <= 1'd0;
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din_dout_toggle_m2 <= 1'd0;
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din_dout_toggle_m3 <= 1'd0;
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din_wr <= 1'd0;
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din_waddr <= 'd0;
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din_enable <= 1'd0;
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din_toggle <= 1'd0;
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end else begin
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din_dout_toggle_m1 <= dout_toggle;
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din_dout_toggle_m2 <= din_dout_toggle_m1;
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din_dout_toggle_m3 <= din_dout_toggle_m2;
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din_wr <= din_valid & din_enable;
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if (din_dout_toggle_s == 1'b1) begin
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din_waddr <= 'd0;
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din_enable <= 1'b1;
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end else if (din_wr == 1'b1) begin
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din_waddr <= din_waddr + 1'b1;
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if (din_waddr_max_s == 1) begin
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din_enable <= 1'b0;
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end
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end
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if ((din_wr == 1'b1) && (din_waddr_max_s == 1)) begin
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din_toggle <= ~din_toggle;
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end
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end
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end
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// read interface
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assign dout_raddr_max_s = & dout_raddr;
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assign dout_rd_s = (dout_cnt == 5'd0) ? dout_enable : 1'b0;
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assign dout_din_toggle_s = dout_din_toggle_m3 ^ dout_din_toggle_m2;
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always @(posedge dout_clk or posedge dout_rst) begin
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if (dout_rst == 1'b1) begin
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dout_din_toggle_m1 <= 1'd0;
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dout_din_toggle_m2 <= 1'd0;
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dout_din_toggle_m3 <= 1'd0;
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dout_cnt <= 'd0;
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dout_ld <= 'd0;
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dout_ld_d <= 'd0;
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dout_raddr <= 'd0;
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dout_enable <= 1'd0;
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dout_toggle <= 1'd1;
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end else begin
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dout_din_toggle_m1 <= din_toggle;
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dout_din_toggle_m2 <= dout_din_toggle_m1;
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dout_din_toggle_m3 <= dout_din_toggle_m2;
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if ((dout_din_toggle_s == 1'b1) || (dout_cnt >= ((DIN_DATA_WIDTH/16) - 1))) begin
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dout_cnt <= 'd0;
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end else begin
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dout_cnt <= dout_cnt + 1'b1;
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end
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dout_ld <= | dout_cnt;
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dout_ld_d <= dout_ld;
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if (dout_din_toggle_s == 1'b1) begin
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dout_raddr <= 'd0;
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dout_enable <= 1'b1;
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end else if (dout_rd_s == 1'b1) begin
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dout_raddr <= dout_raddr + 1'b1;
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if (dout_raddr_max_s == 1'b1) begin
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dout_enable <= 1'b0;
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end
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end
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if ((dout_rd_s == 1'b1) && (dout_raddr_max_s == 1'b1)) begin
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dout_toggle <= ~dout_toggle;
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end
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end
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end
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always @(posedge dout_clk or posedge dout_rst) begin
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if (dout_rst == 1'b1) begin
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dout_valid <= 'd0;
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dout_rdata_0 <= 'd0;
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dout_rdata_1 <= 'd0;
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dout_rdata_2 <= 'd0;
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dout_rdata_3 <= 'd0;
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dout_rdata_4 <= 'd0;
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dout_rdata_5 <= 'd0;
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dout_rdata_6 <= 'd0;
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dout_rdata_7 <= 'd0;
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end else begin
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if (dout_ld_d == 1'b0) begin
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dout_valid <= dout_enable;
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dout_rdata_0 <= dout_rdata_s[0];
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dout_rdata_1 <= dout_rdata_s[1];
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dout_rdata_2 <= dout_rdata_s[2];
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dout_rdata_3 <= dout_rdata_s[3];
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dout_rdata_4 <= dout_rdata_s[4];
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dout_rdata_5 <= dout_rdata_s[5];
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dout_rdata_6 <= dout_rdata_s[6];
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dout_rdata_7 <= dout_rdata_s[7];
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end else begin
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dout_valid <= dout_valid;
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dout_rdata_0 <= {16'd0, dout_rdata_0[(DIN_DATA_WIDTH-1):16]};
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dout_rdata_1 <= {16'd0, dout_rdata_1[(DIN_DATA_WIDTH-1):16]};
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dout_rdata_2 <= {16'd0, dout_rdata_2[(DIN_DATA_WIDTH-1):16]};
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dout_rdata_3 <= {16'd0, dout_rdata_3[(DIN_DATA_WIDTH-1):16]};
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dout_rdata_4 <= {16'd0, dout_rdata_4[(DIN_DATA_WIDTH-1):16]};
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dout_rdata_5 <= {16'd0, dout_rdata_5[(DIN_DATA_WIDTH-1):16]};
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dout_rdata_6 <= {16'd0, dout_rdata_6[(DIN_DATA_WIDTH-1):16]};
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dout_rdata_7 <= {16'd0, dout_rdata_7[(DIN_DATA_WIDTH-1):16]};
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end
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end
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end
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assign dout_data_0 = dout_rdata_0[15:0];
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assign dout_data_1 = dout_rdata_1[15:0];
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assign dout_data_2 = dout_rdata_2[15:0];
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assign dout_data_3 = dout_rdata_3[15:0];
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assign dout_data_4 = dout_rdata_4[15:0];
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assign dout_data_5 = dout_rdata_5[15:0];
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assign dout_data_6 = dout_rdata_6[15:0];
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assign dout_data_7 = dout_rdata_7[15:0];
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// instantiations
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generate
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if (NUM_OF_CHANNELS < 8) begin
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for (n = NUM_OF_CHANNELS; n < 8; n = n + 1) begin: g_channels_unused
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assign dout_rdata_s[n] = 'd0;
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end
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end
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for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_channels
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ad_mem #(
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.ADDRESS_WIDTH (ADDRESS_WIDTH),
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.DATA_WIDTH (DIN_DATA_WIDTH))
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i_mem (
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.clka (din_clk),
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.wea (din_wr),
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.addra (din_waddr),
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.dina (din_wdata_s[n]),
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.clkb (dout_clk),
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.addrb (dout_raddr),
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.doutb (dout_rdata_s[n]));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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