305 lines
9.2 KiB
Verilog
305 lines
9.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9371_rx #(
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parameter DATAPATH_DISABLE = 0,
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parameter ID = 0) (
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// adc interface
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output adc_rst,
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input adc_clk,
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input [ 63:0] adc_data,
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// dma interface
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output adc_enable_i0,
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output adc_valid_i0,
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output [ 15:0] adc_data_i0,
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output adc_enable_q0,
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output adc_valid_q0,
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output [ 15:0] adc_data_q0,
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output adc_enable_i1,
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output adc_valid_i1,
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output [ 15:0] adc_data_i1,
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output adc_enable_q1,
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output adc_valid_q1,
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output [ 15:0] adc_data_q1,
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input adc_dovf,
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input adc_dunf,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [ 13:0] up_waddr,
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input [ 31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [ 13:0] up_raddr,
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output reg [ 31:0] up_rdata,
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output reg up_rack);
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// internal registers
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reg up_status_pn_err = 'd0;
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reg up_status_pn_oos = 'd0;
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reg up_status_or = 'd0;
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// internal signals
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wire [ 15:0] adc_data_iq_i0_s;
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wire [ 15:0] adc_data_iq_q0_s;
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wire [ 15:0] adc_data_iq_i1_s;
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wire [ 15:0] adc_data_iq_q1_s;
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wire [ 3:0] up_adc_pn_err_s;
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wire [ 3:0] up_adc_pn_oos_s;
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wire [ 3:0] up_adc_or_s;
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wire [ 4:0] up_wack_s;
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wire [ 4:0] up_rack_s;
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wire [ 31:0] up_rdata_s[0:4];
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_status_pn_err <= 'd0;
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up_status_pn_oos <= 'd0;
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up_status_or <= 'd0;
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_status_pn_err <= | up_adc_pn_err_s;
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up_status_pn_oos <= | up_adc_pn_oos_s;
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up_status_or <= | up_adc_or_s;
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up_wack <= | up_wack_s;
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up_rack <= | up_rack_s;
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
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end
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end
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// channel width is 32 bits
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assign adc_valid_i0 = 1'b1;
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assign adc_valid_q0 = 1'b1;
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assign adc_valid_i1 = 1'b1;
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assign adc_valid_q1 = 1'b1;
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// channel 0 (i)
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axi_ad9371_rx_channel #(
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.Q_OR_I_N (0),
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.COMMON_ID ('h01),
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.CHANNEL_ID (0),
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.DATAPATH_DISABLE (DATAPATH_DISABLE),
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.DATA_WIDTH (16))
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i_rx_channel_0 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid_in (1'b1),
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.adc_data_in (adc_data[15:0]),
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.adc_valid_out (),
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.adc_data_out (adc_data_i0),
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.adc_data_iq_in (adc_data_iq_q0_s),
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.adc_data_iq_out (adc_data_iq_i0_s),
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.adc_enable (adc_enable_i0),
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.up_adc_pn_err (up_adc_pn_err_s[0]),
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.up_adc_pn_oos (up_adc_pn_oos_s[0]),
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.up_adc_or (up_adc_or_s[0]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0]));
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// channel 1 (q)
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axi_ad9371_rx_channel #(
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.Q_OR_I_N (1),
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.COMMON_ID ('h01),
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.CHANNEL_ID (1),
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.DATAPATH_DISABLE (DATAPATH_DISABLE),
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.DATA_WIDTH (16))
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i_rx_channel_1 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid_in (1'b1),
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.adc_data_in (adc_data[31:16]),
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.adc_valid_out (),
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.adc_data_out (adc_data_q0),
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.adc_data_iq_in (adc_data_iq_i0_s),
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.adc_data_iq_out (adc_data_iq_q0_s),
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.adc_enable (adc_enable_q0),
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.up_adc_pn_err (up_adc_pn_err_s[1]),
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.up_adc_pn_oos (up_adc_pn_oos_s[1]),
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.up_adc_or (up_adc_or_s[1]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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// channel 2 (i)
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axi_ad9371_rx_channel #(
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.Q_OR_I_N (0),
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.COMMON_ID ('h01),
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.CHANNEL_ID (2),
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.DATAPATH_DISABLE (DATAPATH_DISABLE),
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.DATA_WIDTH (16))
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i_rx_channel_2 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid_in (1'b1),
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.adc_data_in (adc_data[47:32]),
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.adc_valid_out (),
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.adc_data_out (adc_data_i1),
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.adc_data_iq_in (adc_data_iq_q1_s),
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.adc_data_iq_out (adc_data_iq_i1_s),
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.adc_enable (adc_enable_i1),
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.up_adc_pn_err (up_adc_pn_err_s[2]),
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.up_adc_pn_oos (up_adc_pn_oos_s[2]),
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.up_adc_or (up_adc_or_s[2]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[2]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[2]),
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.up_rack (up_rack_s[2]));
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// channel 3 (q)
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axi_ad9371_rx_channel #(
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.Q_OR_I_N (1),
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.COMMON_ID ('h01),
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.CHANNEL_ID (3),
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.DATAPATH_DISABLE (DATAPATH_DISABLE),
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.DATA_WIDTH (16))
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i_rx_channel_3 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid_in (1'b1),
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.adc_data_in (adc_data[63:48]),
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.adc_valid_out (),
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.adc_data_out (adc_data_q1),
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.adc_data_iq_in (adc_data_iq_i1_s),
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.adc_data_iq_out (adc_data_iq_q1_s),
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.adc_enable (adc_enable_q1),
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.up_adc_pn_err (up_adc_pn_err_s[3]),
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.up_adc_pn_oos (up_adc_pn_oos_s[3]),
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.up_adc_or (up_adc_or_s[3]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[3]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[3]),
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.up_rack (up_rack_s[3]));
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// common processor control
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up_adc_common #(
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.COMMON_ID ('h00),
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.ID (ID))
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i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status (1'b1),
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.adc_sync_status (1'd0),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (adc_dunf),
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.adc_clk_ratio (32'd1),
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.adc_start_code (),
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.adc_sync (),
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_oos (up_status_pn_oos),
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.up_status_or (up_status_or),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (32'd0),
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.up_drp_ready (1'd0),
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.up_drp_locked (1'd1),
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.up_usr_chanmax_out (),
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.up_usr_chanmax_in (8'd3),
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.up_adc_gpio_in (32'd0),
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.up_adc_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[4]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[4]),
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.up_rack (up_rack_s[4]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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