319 lines
11 KiB
Verilog
319 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_jesd_xcvr (
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rst,
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// receive interface
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rx_clk,
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rx_rstn,
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rx_ext_sysref_in,
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rx_ext_sysref_out,
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rx_sync,
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rx_sof,
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rx_data,
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rx_ready,
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rx_ip_sysref,
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rx_ip_sync,
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rx_ip_sof,
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rx_ip_valid,
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rx_ip_data,
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rx_ip_ready,
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// transmit interface
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tx_clk,
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tx_rstn,
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tx_ext_sysref_in,
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tx_ext_sysref_out,
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tx_sync,
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tx_data,
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tx_ready,
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tx_ip_sysref,
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tx_ip_sync,
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tx_ip_valid,
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tx_ip_data,
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tx_ip_ready,
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// axi-lite (slave)
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awprot,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arprot,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rready);
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parameter ID = 0;
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parameter DEVICE_TYPE = 0;
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parameter TX_NUM_OF_LANES = 4;
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parameter RX_NUM_OF_LANES = 4;
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localparam TX_LANECNT = (TX_NUM_OF_LANES == 0) ? 1 : TX_NUM_OF_LANES;
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localparam RX_LANECNT = (RX_NUM_OF_LANES == 0) ? 1 : RX_NUM_OF_LANES;
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output rst;
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// receive interface
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input rx_clk;
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output rx_rstn;
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input rx_ext_sysref_in;
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output rx_ext_sysref_out;
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output rx_sync;
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output [((RX_LANECNT* 1)-1):0] rx_sof;
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output [((RX_LANECNT*32)-1):0] rx_data;
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input [((RX_LANECNT* 1)-1):0] rx_ready;
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output rx_ip_sysref;
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input rx_ip_sync;
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input [ 3:0] rx_ip_sof;
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input rx_ip_valid;
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input [((RX_LANECNT*32)-1):0] rx_ip_data;
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output rx_ip_ready;
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// transmit interface
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input tx_clk;
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output tx_rstn;
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input tx_ext_sysref_in;
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output tx_ext_sysref_out;
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input tx_sync;
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input [((TX_LANECNT*32)-1):0] tx_data;
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input [((TX_LANECNT* 1)-1):0] tx_ready;
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output tx_ip_sysref;
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output tx_ip_sync;
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output tx_ip_valid;
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output [((TX_LANECNT*32)-1):0] tx_ip_data;
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input tx_ip_ready;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [ 31:0] s_axi_awaddr;
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input [ 2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_wvalid;
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input [ 31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [ 31:0] s_axi_araddr;
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input [ 2:0] s_axi_arprot;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 31:0] s_axi_rdata;
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output [ 1:0] s_axi_rresp;
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input s_axi_rready;
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// internal signals
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wire up_rstn;
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wire up_clk;
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wire [ 7:0] status_s;
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wire [ 3:0] rx_ip_sof_s;
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wire [((RX_LANECNT*32)-1):0] rx_ip_data_s;
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wire [ 7:0] rx_status_s;
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wire [ 7:0] tx_status_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s;
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wire up_rack_s;
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// variables
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genvar n;
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// assignments
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assign status_s = 8'hff;
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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assign rx_ip_ready = 1'b1;
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assign rx_ip_sysref = rx_ext_sysref_out;
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assign rx_ip_sof_s[3] = rx_ip_sof[0];
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assign rx_ip_sof_s[2] = rx_ip_sof[1];
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assign rx_ip_sof_s[1] = rx_ip_sof[2];
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assign rx_ip_sof_s[0] = rx_ip_sof[3];
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generate
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for (n = 0; n < RX_LANECNT; n = n + 1) begin: g_rx_swap
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assign rx_ip_data_s[((n*32) + 31):((n*32) + 24)] = rx_ip_data[((n*32) + 7):((n*32) + 0)];
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assign rx_ip_data_s[((n*32) + 23):((n*32) + 16)] = rx_ip_data[((n*32) + 15):((n*32) + 8)];
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assign rx_ip_data_s[((n*32) + 15):((n*32) + 8)] = rx_ip_data[((n*32) + 23):((n*32) + 16)];
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assign rx_ip_data_s[((n*32) + 7):((n*32) + 0)] = rx_ip_data[((n*32) + 31):((n*32) + 24)];
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end
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endgenerate
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generate
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if (RX_LANECNT < 8) begin
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assign rx_status_s[7:RX_LANECNT] = status_s[7:RX_LANECNT];
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assign rx_status_s[(RX_LANECNT-1):0] = rx_ready;
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end else begin
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assign rx_status_s = rx_ready[7:0];
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end
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endgenerate
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generate
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for (n = 0; n < RX_LANECNT; n = n + 1) begin: g_rx_align
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ad_jesd_align i_jesd_align (
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.rx_clk (rx_clk),
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.rx_ip_sof (rx_ip_sof_s),
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.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
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.rx_sof (rx_sof[n]),
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.rx_data (rx_data[n*32+31:n*32]));
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end
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endgenerate
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assign tx_ip_valid = 1'b1;
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assign tx_ip_sysref = tx_ext_sysref_out;
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generate
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for (n = 0; n < TX_LANECNT; n = n + 1) begin: g_tx_swap
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assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)];
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assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)];
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assign tx_ip_data[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)];
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assign tx_ip_data[((n*32) + 7):((n*32) + 0)] = tx_data[((n*32) + 31):((n*32) + 24)];
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end
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endgenerate
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generate
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if (TX_LANECNT < 8) begin
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assign tx_status_s[7:TX_LANECNT] = status_s[7:TX_LANECNT];
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assign tx_status_s[(TX_LANECNT-1):0] = tx_ready;
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end else begin
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assign tx_status_s = tx_ready[7:0];
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end
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endgenerate
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// processor
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up_xcvr #(
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.ID(ID),
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.DEVICE_TYPE(DEVICE_TYPE))
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i_up_xcvr (
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.rst (rst),
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.rx_clk (rx_clk),
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.rx_rstn (rx_rstn),
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.rx_ext_sysref (rx_ext_sysref_in),
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.rx_sysref (rx_ext_sysref_out),
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.rx_ip_sync (rx_ip_sync),
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.rx_sync (rx_sync),
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.rx_status (rx_status_s),
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.tx_clk (tx_clk),
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.tx_rstn (tx_rstn),
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.tx_ext_sysref (tx_ext_sysref_in),
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.tx_sysref (tx_ext_sysref_out),
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.tx_sync (tx_sync),
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.tx_ip_sync (tx_ip_sync),
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.tx_status (tx_status_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// axi interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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