401 lines
12 KiB
Verilog
401 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output [ 13:0] ddr3_addr,
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output [ 2:0] ddr3_ba,
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output ddr3_cas_n,
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output [ 0:0] ddr3_ck_n,
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output [ 0:0] ddr3_ck_p,
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output [ 0:0] ddr3_cke,
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output [ 0:0] ddr3_cs_n,
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output [ 7:0] ddr3_dm,
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inout [ 63:0] ddr3_dq,
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inout [ 7:0] ddr3_dqs_n,
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inout [ 7:0] ddr3_dqs_p,
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output [ 0:0] ddr3_odt,
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output ddr3_ras_n,
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output ddr3_reset_n,
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output ddr3_we_n,
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input sgmii_rxp,
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input sgmii_rxn,
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output sgmii_txp,
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output sgmii_txn,
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output phy_rstn,
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input mgt_clk_p,
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input mgt_clk_n,
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output mdio_mdc,
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inout mdio_mdio,
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output fan_pwm,
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output [26:1] linear_flash_addr,
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output linear_flash_adv_ldn,
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output linear_flash_ce_n,
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output linear_flash_oen,
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output linear_flash_wen,
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inout [15:0] linear_flash_dq_io,
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inout [ 6:0] gpio_lcd,
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inout [ 20:0] gpio_bd,
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output iic_rstn,
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inout iic_scl,
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inout iic_sda,
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input rx_ref_clk_0_p,
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input rx_ref_clk_0_n,
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input [ 7:0] rx_data_0_p,
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input [ 7:0] rx_data_0_n,
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input rx_ref_clk_1_p,
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input rx_ref_clk_1_n,
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input [ 7:0] rx_data_1_p,
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input [ 7:0] rx_data_1_n,
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output rx_sysref_p,
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output rx_sysref_n,
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output rx_sync_0_p,
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output rx_sync_0_n,
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output rx_sync_1_p,
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output rx_sync_1_n,
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output spi_csn_0,
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output spi_csn_1,
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output spi_clk,
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inout spi_sdio,
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output spi_dirn,
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output dac_clk,
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output dac_data,
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output dac_sync_0,
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output dac_sync_1,
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output psync_0,
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output psync_1,
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input trig_p,
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input trig_n,
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output vdither_p,
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output vdither_n,
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inout pwr_good,
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inout fd_1,
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inout irq_1,
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inout fd_0,
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inout irq_0,
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inout pwdn_1,
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inout rst_1,
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output drst_1,
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output arst_1,
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inout pwdn_0,
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inout rst_0,
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output drst_0,
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output arst_0);
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// internal registers
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reg [ 4:0] gpio_o_60_56_d = 'd0;
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reg gpio_dld = 'd0;
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reg rx_sysref_m1 = 'd0;
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reg rx_sysref_m2 = 'd0;
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reg rx_sysref_int = 'd0;
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// internal signals
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wire delay_clk;
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wire delay_rst;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire [ 63:0] gpio_t;
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wire [ 7:0] spi_csn;
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wire spi_clk;
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wire spi_mosi;
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wire spi_miso;
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wire rx_clk;
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wire rx_ref_clk_0;
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wire rx_ref_clk_1;
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wire rx_sync_0;
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wire rx_sync_1;
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wire up_rstn;
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wire up_clk;
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// spi
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assign iic_rstn = 1'b1;
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assign fan_pwm = 1'b1;
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assign dac_clk = spi_clk;
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assign dac_data = spi_mosi;
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assign dac_sync_1 = spi_csn[3];
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assign dac_sync_0 = spi_csn[2];
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assign spi_csn_1 = spi_csn[1];
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assign spi_csn_0 = spi_csn[0];
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assign drst_1 = 1'b0;
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assign arst_1 = 1'b0;
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assign drst_0 = 1'b0;
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assign arst_0 = 1'b0;
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// sysref iob
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always @(posedge up_clk or negedge up_rstn) begin
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if (up_rstn == 1'b0) begin
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gpio_o_60_56_d <= 5'd0;
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gpio_dld <= 1'b0;
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end else begin
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gpio_o_60_56_d <= gpio_o[60:56];
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if (gpio_o[60:56] == gpio_o_60_56_d) begin
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gpio_dld <= 1'b0;
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end else begin
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gpio_dld <= 1'b1;
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end
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end
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end
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// sysref internal
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always @(posedge rx_clk) begin
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rx_sysref_m1 <= gpio_o[32];
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rx_sysref_m2 <= rx_sysref_m1;
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rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
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end
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// instantiations
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ad_lvds_out #(
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.DEVICE_TYPE (0),
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.SINGLE_ENDED (0),
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.IODELAY_ENABLE (1),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"))
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i_rx_sysref (
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.tx_clk (rx_clk),
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.tx_data_p (rx_sysref_int),
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.tx_data_n (rx_sysref_int),
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.tx_data_out_p (rx_sysref_p),
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.tx_data_out_n (rx_sysref_n),
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.up_clk (up_clk),
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.up_dld (gpio_dld),
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.up_dwdata (gpio_o[60:56]),
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.up_drdata (gpio_i[60:56]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (gpio_i[61]));
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IBUFDS_GTE2 i_ibufds_rx_ref_clk_0 (
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.CEB (1'd0),
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.I (rx_ref_clk_0_p),
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.IB (rx_ref_clk_0_n),
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.O (rx_ref_clk_0),
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.ODIV2 ());
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IBUFDS_GTE2 i_ibufds_rx_ref_clk_1 (
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.CEB (1'd0),
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.I (rx_ref_clk_1_p),
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.IB (rx_ref_clk_1_n),
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.O (rx_ref_clk_1),
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.ODIV2 ());
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OBUFDS i_obufds_rx_sync_0 (
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.I (rx_sync_0),
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.O (rx_sync_0_p),
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.OB (rx_sync_0_n));
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OBUFDS i_obufds_rx_sync_1 (
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.I (rx_sync_1),
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.O (rx_sync_1_p),
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.OB (rx_sync_1_n));
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IBUFDS i_ibufds_trig (
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.I (trig_p),
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.IB (trig_n),
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.O (gpio_i[46]));
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OBUFDS i_obufds_vdither (
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.I (gpio_o[45]),
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.O (vdither_p),
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.OB (vdither_n));
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fmcadc5_psync i_fmcadc5_psync (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.psync_0 (psync_0),
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.psync_1 (psync_1));
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fmcadc5_spi i_fmcadc5_spi (
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.spi_csn_0 (spi_csn[0]),
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.spi_csn_1 (spi_csn[1]),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio),
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.spi_dirn (spi_dirn));
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ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
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.dio_t ({gpio_t[44:40], gpio_t[39:38], gpio_t[35:34]}),
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.dio_i ({gpio_o[44:40], gpio_o[39:38], gpio_o[35:34]}),
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.dio_o ({gpio_i[44:40], gpio_i[39:38], gpio_i[35:34]}),
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.dio_p ({ pwr_good, // 44
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fd_1, // 43
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irq_1, // 42
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fd_0, // 41
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irq_0, // 40
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pwdn_1, // 39
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rst_1, // 38
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pwdn_0, // 35
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rst_0})); // 34
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ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
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.dio_t (gpio_t[20:0]),
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.dio_i (gpio_o[20:0]),
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.dio_o (gpio_i[20:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio_lcd_tri_io (gpio_lcd),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.linear_flash_addr (linear_flash_addr),
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.linear_flash_adv_ldn (linear_flash_adv_ldn),
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.linear_flash_ce_n (linear_flash_ce_n),
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.linear_flash_dq_io(linear_flash_dq_io),
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.linear_flash_oen (linear_flash_oen),
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.linear_flash_wen (linear_flash_wen),
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.mb_intr_06 (1'b0),
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.mb_intr_07 (1'b0),
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.mb_intr_08 (1'b0),
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.mb_intr_13 (1'b0),
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.mb_intr_14 (1'b0),
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.mb_intr_15 (1'b0),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.mgt_clk_clk_n (mgt_clk_n),
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.mgt_clk_clk_p (mgt_clk_p),
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.phy_rstn (phy_rstn),
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.phy_sd (1'b1),
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.rx_clk (rx_clk),
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.rx_data_0_n (rx_data_0_n[0]),
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.rx_data_0_p (rx_data_0_p[0]),
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.rx_data_1_0_n (rx_data_1_n[0]),
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.rx_data_1_0_p (rx_data_1_p[0]),
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.rx_data_1_1_n (rx_data_1_n[1]),
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.rx_data_1_1_p (rx_data_1_p[1]),
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.rx_data_1_2_n (rx_data_1_n[2]),
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.rx_data_1_2_p (rx_data_1_p[2]),
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.rx_data_1_3_n (rx_data_1_n[3]),
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.rx_data_1_3_p (rx_data_1_p[3]),
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.rx_data_1_4_n (rx_data_1_n[4]),
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.rx_data_1_4_p (rx_data_1_p[4]),
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.rx_data_1_5_n (rx_data_1_n[5]),
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.rx_data_1_5_p (rx_data_1_p[5]),
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.rx_data_1_6_n (rx_data_1_n[6]),
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.rx_data_1_6_p (rx_data_1_p[6]),
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.rx_data_1_7_n (rx_data_1_n[7]),
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.rx_data_1_7_p (rx_data_1_p[7]),
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.rx_data_1_n (rx_data_0_n[1]),
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.rx_data_1_p (rx_data_0_p[1]),
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.rx_data_2_n (rx_data_0_n[2]),
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.rx_data_2_p (rx_data_0_p[2]),
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.rx_data_3_n (rx_data_0_n[3]),
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.rx_data_3_p (rx_data_0_p[3]),
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.rx_data_4_n (rx_data_0_n[4]),
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.rx_data_4_p (rx_data_0_p[4]),
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.rx_data_5_n (rx_data_0_n[5]),
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.rx_data_5_p (rx_data_0_p[5]),
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.rx_data_6_n (rx_data_0_n[6]),
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.rx_data_6_p (rx_data_0_p[6]),
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.rx_data_7_n (rx_data_0_n[7]),
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.rx_data_7_p (rx_data_0_p[7]),
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.rx_ref_clk_0 (rx_ref_clk_0),
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.rx_ref_clk_1 (rx_ref_clk_1),
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.rx_sync_0 (rx_sync_0),
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.rx_sync_1_0 (rx_sync_1),
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.rx_sysref_0 (rx_sysref_int),
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.rx_sysref_1_0 (rx_sysref_int),
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.sgmii_rxn (sgmii_rxn),
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.sgmii_rxp (sgmii_rxp),
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.sgmii_txn (sgmii_txn),
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.sgmii_txp (sgmii_txp),
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.spi_clk_i (1'b0),
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.spi_clk_o (spi_clk),
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.spi_csn_i (8'hff),
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.spi_csn_o (spi_csn),
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.spi_sdi_i (spi_miso),
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.spi_sdo_i (1'b0),
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.spi_sdo_o (spi_mosi),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.up_clk (up_clk),
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.up_rstn (up_rstn));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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