129 lines
6.7 KiB
Tcl
129 lines
6.7 KiB
Tcl
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# adc peripherals
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set axi_ad9250_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9250_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9250_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9250_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9250_xcvr
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set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9250_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd
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set data_bsplit [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 data_bsplit]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64} ] $data_bsplit
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_bsplit
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set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
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set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
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set axi_ad9250_0_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9250_0_cpack]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9250_0_cpack
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set axi_ad9250_1_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9250_1_cpack]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9250_1_cpack
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set axi_ad9250_0_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_0_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.ID {0}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_0_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_0_dma
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set axi_ad9250_1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_1_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.ID {0}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma
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# transceiver core
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set util_fmcjesdadc1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcjesdadc1_xcvr]
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcjesdadc1_xcvr
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ad_connect sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn
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ad_connect sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk
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# connections (adc)
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ad_xcvrcon util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk
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ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_0_core/rx_sof
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk
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ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_1_core/rx_sof
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ad_connect axi_ad9250_jesd/rx_tdata data_bsplit/data
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ad_connect axi_ad9250_0_core/rx_data data_bsplit/split_data_0
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ad_connect axi_ad9250_1_core/rx_data data_bsplit/split_data_1
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_cpack/adc_clk
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_cpack/adc_clk
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ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_0_cpack/adc_rst
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ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_1_cpack/adc_rst
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ad_connect axi_ad9250_0_core/adc_enable_a axi_ad9250_0_cpack/adc_enable_0
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ad_connect axi_ad9250_0_core/adc_valid_a axi_ad9250_0_cpack/adc_valid_0
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ad_connect axi_ad9250_0_core/adc_data_a axi_ad9250_0_cpack/adc_data_0
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ad_connect axi_ad9250_0_core/adc_enable_b axi_ad9250_0_cpack/adc_enable_1
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ad_connect axi_ad9250_0_core/adc_valid_b axi_ad9250_0_cpack/adc_valid_1
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ad_connect axi_ad9250_0_core/adc_data_b axi_ad9250_0_cpack/adc_data_1
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ad_connect axi_ad9250_1_core/adc_enable_a axi_ad9250_1_cpack/adc_enable_0
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ad_connect axi_ad9250_1_core/adc_valid_a axi_ad9250_1_cpack/adc_valid_0
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ad_connect axi_ad9250_1_core/adc_data_a axi_ad9250_1_cpack/adc_data_0
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ad_connect axi_ad9250_1_core/adc_enable_b axi_ad9250_1_cpack/adc_enable_1
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ad_connect axi_ad9250_1_core/adc_valid_b axi_ad9250_1_cpack/adc_valid_1
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ad_connect axi_ad9250_1_core/adc_data_b axi_ad9250_1_cpack/adc_data_1
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ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk
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ad_connect axi_ad9250_0_dma/fifo_wr_en axi_ad9250_0_cpack/adc_valid
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ad_connect axi_ad9250_0_dma/fifo_wr_sync axi_ad9250_0_cpack/adc_sync
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ad_connect axi_ad9250_0_dma/fifo_wr_din axi_ad9250_0_cpack/adc_data
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ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow
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ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk
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ad_connect axi_ad9250_1_dma/fifo_wr_en axi_ad9250_1_cpack/adc_valid
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ad_connect axi_ad9250_1_dma/fifo_wr_sync axi_ad9250_1_cpack/adc_sync
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ad_connect axi_ad9250_1_dma/fifo_wr_din axi_ad9250_1_cpack/adc_data
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ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad9250_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad9250_0_core
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ad_cpu_interconnect 0x44A20000 axi_ad9250_1_core
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ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9250_0_dma
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ad_cpu_interconnect 0x7c430000 axi_ad9250_1_dma
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# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad9250_xcvr/m_axi
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# interconnect (adc)
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ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_0_dma/m_dest_axi
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ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_1_dma/m_dest_axi
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ad_connect sys_cpu_resetn axi_ad9250_0_dma/m_dest_axi_aresetn
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ad_connect sys_cpu_resetn axi_ad9250_1_dma/m_dest_axi_aresetn
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#interrupts
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ad_cpu_interrupt ps-13 mb-13 axi_ad9250_0_dma/irq
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ad_cpu_interrupt ps-12 mb-12 axi_ad9250_1_dma/irq
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