273 lines
8.6 KiB
Verilog
273 lines
8.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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// This core supports the following CFTL pmods:
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// - EVAL-CN0350-PMDZ
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// - EVAL-CN0335-PMDZ
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// - EVAL-CN0336-PMDZ
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// - EVAL-CN0337-PMDZ
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//
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// It controls a simple three wire SPI interface with an additional control
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// line for conversion start, and a counter which trigger the SPI read after
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// the end of ADC conversion.
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// NOTE: - The maximum frequency of serial read clock (adc_spi_clk) is 50Mhz.
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// - The maximum conversion rate is 1MSPS (AD7091r)
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// - The frequency of the serial read clock need to be adjusted to the desired
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// conversion rate, exp. for AD7091r :
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//
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// ADC Rate >= ADC Conversion Time + SPI Word Length * ADC Serial Clock Period + Tquiet
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// where ADC Conversion Time >= 650ns
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// SPI Word Length = 12
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// Tquiet >= 58ns
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`timescale 1ns/1ns
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module util_pmod_adc #(
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parameter FPGA_CLOCK_MHZ = 100,
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parameter ADC_CONVST_NS = 100,
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parameter ADC_CONVERT_NS = 650,
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parameter ADC_TQUIET_NS = 60,
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parameter SPI_WORD_LENGTH = 12,
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parameter ADC_RESET_LENGTH = 3,
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parameter ADC_CLK_DIVIDE = 16) (
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// clock and reset signals
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input clk,
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input resetn,
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// dma interface
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output reg [15:0] adc_data,
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output reg adc_valid,
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output reg [24:0] adc_dbg,
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// adc interface (clk, data, cs and conversion start)
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input adc_sdo,
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output adc_sclk,
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output reg adc_cs_n,
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output reg adc_convst_n);
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localparam ADC_POWERUP = 0;
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localparam ADC_SW_RESET = 1;
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localparam ADC_IDLE = 2;
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localparam ADC_START_CNV = 3;
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localparam ADC_WAIT_CNV_DONE = 4;
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localparam ADC_READ_CNV_RESULT = 5;
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localparam ADC_DATA_VALID = 6;
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localparam ADC_TQUIET = 7;
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localparam [15:0] FPGA_CLOCK_PERIOD_NS = 1000 / FPGA_CLOCK_MHZ;
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localparam [15:0] ADC_CONVST_CNT = ADC_CONVST_NS / FPGA_CLOCK_PERIOD_NS;
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localparam [15:0] ADC_CONVERT_CNT = ADC_CONVERT_NS / FPGA_CLOCK_PERIOD_NS;
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localparam [15:0] ADC_TQUITE_CNT = ADC_TQUIET_NS / FPGA_CLOCK_PERIOD_NS;
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// Internal registers
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reg [ 2:0] adc_state = 3'b0; // current state for the ADC control state machine
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reg [ 2:0] adc_next_state = 3'b0; // next state for the ADC control state machine
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reg [15:0] adc_tconvst_cnt = 16'b0;
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reg [15:0] adc_tconvert_cnt = 16'b0;
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reg [15:0] adc_tquiet_cnt = 16'b0;
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reg [15:0] sclk_clk_cnt = 16'b0;
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reg [15:0] sclk_clk_cnt_m1 = 16'b0;
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reg [7:0] adc_clk_cnt = 8'h0;
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reg adc_clk_en = 1'b0;
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reg adc_sw_reset = 1'b0;
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reg data_rd_ready = 1'b0;
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reg adc_spi_clk = 1'b0;
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// Assign/Always Blocks
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assign adc_sclk = adc_spi_clk & adc_clk_en;
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// spi clock generation
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always @(posedge clk) begin
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adc_clk_cnt <= adc_clk_cnt + 1;
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if (adc_clk_cnt == ((ADC_CLK_DIVIDE/2)-1)) begin
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adc_clk_cnt <= 0;
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adc_spi_clk <= ~adc_spi_clk;
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end
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end
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// update the ADC timing counters
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always @(posedge clk)
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begin
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if(resetn == 1'b0) begin
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adc_tconvst_cnt <= ADC_CONVST_CNT;
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adc_tconvert_cnt <= ADC_CONVERT_CNT;
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adc_tquiet_cnt <= ADC_TQUITE_CNT;
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end else begin
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if(adc_state == ADC_START_CNV) begin
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adc_tconvst_cnt <= adc_tconvst_cnt - 1;
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end else begin
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adc_tconvst_cnt <= ADC_CONVST_CNT;
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end
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if((adc_state == ADC_START_CNV) || (adc_state == ADC_WAIT_CNV_DONE)) begin
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adc_tconvert_cnt <= adc_tconvert_cnt - 1;
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end else begin
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adc_tconvert_cnt <= ADC_CONVERT_CNT;
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end
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if(adc_state == ADC_TQUIET) begin
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adc_tquiet_cnt <= adc_tquiet_cnt - 1;
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end else begin
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adc_tquiet_cnt <= ADC_TQUITE_CNT;
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end
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end
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end
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// determine when the ADC clock is valid
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always @(negedge adc_spi_clk) begin
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adc_clk_en <= ((adc_state == ADC_READ_CNV_RESULT) && (sclk_clk_cnt != 0)) ? 1'b1 : 1'b0;
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end
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// read data from the ADC
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always @(negedge adc_spi_clk) begin
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sclk_clk_cnt_m1 <= sclk_clk_cnt;
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if((adc_clk_en == 1'b1) && (sclk_clk_cnt != 0)) begin
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adc_data <= {3'b0, adc_data[11:0], adc_sdo};
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if ((adc_sw_reset == 1'b1) && (sclk_clk_cnt == SPI_WORD_LENGTH - ADC_RESET_LENGTH + 1)) begin
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sclk_clk_cnt <= 16'b0;
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end else begin
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sclk_clk_cnt <= sclk_clk_cnt - 1;
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end
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end
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else if(adc_state != ADC_READ_CNV_RESULT) begin
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adc_data <= 16'h0;
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sclk_clk_cnt <= SPI_WORD_LENGTH - 1;
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end
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end
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// update the ADC current state and the control signals
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always @(posedge clk) begin
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if(resetn == 1'b0) begin
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adc_state <= ADC_SW_RESET;
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adc_dbg <= 1'b0;
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end
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else begin
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adc_state <= adc_next_state;
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adc_dbg <= {adc_state, adc_clk_en, sclk_clk_cnt};
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case (adc_state)
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ADC_POWERUP: begin
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adc_convst_n <= 1'b1;
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adc_cs_n <= 1'b1;
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adc_valid <= 1'b0;
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adc_sw_reset <= 1'b0;
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end
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ADC_SW_RESET: begin
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adc_convst_n <= 1'b1;
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adc_cs_n <= 1'b1;
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adc_valid <= 1'b0;
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adc_sw_reset <= 1'b1;
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end
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ADC_IDLE: begin
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adc_convst_n <= 1'b1;
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adc_cs_n <= 1'b1;
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adc_valid <= 1'b0;
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adc_sw_reset <= 1'b0;
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end
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ADC_START_CNV: begin
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adc_convst_n <= 1'b0;
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adc_cs_n <= 1'b1;
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adc_valid <= 1'b0;
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end
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ADC_WAIT_CNV_DONE: begin
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adc_convst_n <= 1'b1;
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adc_cs_n <= 1'b1;
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adc_valid <= 1'b0;
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end
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ADC_READ_CNV_RESULT: begin
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adc_convst_n <= 1'b1;
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adc_cs_n <= 1'b0;
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adc_valid <= 1'b0;
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end
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ADC_DATA_VALID: begin
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adc_convst_n <= 1'b1;
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adc_cs_n <= 1'b0;
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adc_valid <= 1'b1;
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end
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ADC_TQUIET: begin
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adc_convst_n <= 1'b1;
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adc_cs_n <= 1'b1;
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adc_valid <= 1'b0;
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end
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endcase
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end
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end
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// update the ADC next state
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always @(adc_state, adc_tconvst_cnt, adc_tconvert_cnt, sclk_clk_cnt_m1, adc_tquiet_cnt, adc_sw_reset) begin
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adc_next_state <= adc_state;
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case (adc_state)
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ADC_POWERUP: begin
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if(adc_sw_reset == 1'b1) begin
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adc_next_state <= ADC_SW_RESET;
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end
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end
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ADC_SW_RESET: begin
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adc_next_state <= ADC_START_CNV;
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end
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ADC_IDLE: begin
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adc_next_state <= ADC_START_CNV;
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end
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ADC_START_CNV: begin
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if(adc_tconvst_cnt == 0) begin
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adc_next_state <= ADC_WAIT_CNV_DONE;
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end
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end
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ADC_WAIT_CNV_DONE: begin
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if(adc_tconvert_cnt == 0) begin
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adc_next_state <= ADC_READ_CNV_RESULT;
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end
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end
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ADC_READ_CNV_RESULT: begin
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if(sclk_clk_cnt_m1 == 0) begin
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adc_next_state <= ADC_DATA_VALID;
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end
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end
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ADC_DATA_VALID: begin
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adc_next_state <= ADC_TQUIET;
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end
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ADC_TQUIET: begin
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if(adc_tquiet_cnt == 0) begin
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adc_next_state <= ADC_IDLE;
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end
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end
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default: begin
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adc_next_state <= ADC_IDLE;
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end
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endcase
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end
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endmodule
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