360 lines
14 KiB
Verilog
360 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2016(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module avl_dacfifo_rd #(
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parameter AVL_DATA_WIDTH = 512,
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parameter DAC_DATA_WIDTH = 64,
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parameter AVL_DDR_BASE_ADDRESS = 0,
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parameter AVL_DDR_ADDRESS_LIMIT = 1048576,
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parameter DAC_MEM_ADDRESS_WIDTH = 8)(
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input dac_clk,
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input dac_reset,
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input dac_valid,
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output reg [(DAC_DATA_WIDTH-1):0] dac_data,
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output reg dac_xfer_req,
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output reg dac_dunf,
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input avl_clk,
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input avl_reset,
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output reg [24:0] avl_address,
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output reg [ 5:0] avl_burstcount,
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output reg [63:0] avl_byteenable,
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input avl_ready,
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input avl_readdatavalid,
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output reg avl_read,
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input [AVL_DATA_WIDTH-1:0] avl_data,
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input [24:0] avl_last_address,
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input [63:0] avl_last_byteenable,
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input avl_xfer_req);
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// Max supported MEM_RATIO is 16
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localparam MEM_RATIO = AVL_DATA_WIDTH/DAC_DATA_WIDTH;
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localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH :
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(MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) :
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(MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) :
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(MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) :
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(DAC_MEM_ADDRESS_WIDTH - 4);
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localparam AVL_MEM_THRESHOLD_LO = 8;
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localparam AVL_MEM_THRESHOLD_HI = {(AVL_MEM_ADDRESS_WIDTH){1'b1}} - 7;
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// internal register
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address_g;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_m1;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_m2;
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reg avl_mem_wr_enable;
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reg avl_mem_request_data;
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reg [AVL_DATA_WIDTH-1:0] avl_mem_data;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_address_diff;
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reg avl_xfer_req_d;
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reg avl_xfer_req_dd;
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reg avl_read_inprogress;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_wr_address;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_wr_address_m2;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_wr_address_m1;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_rd_address;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_rd_address_g;
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reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_address_diff;
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reg dac_avl_xfer_req;
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reg dac_avl_xfer_req_m1;
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reg dac_avl_xfer_req_m2;
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// internal signals
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wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_s;
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wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_address_diff_s;
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wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_address_diff_s;
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wire avl_xfer_req_init_s;
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wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_wr_address_s;
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wire dac_mem_rd_enable_s;
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wire [DAC_DATA_WIDTH-1:0] dac_mem_data_s;
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// ==========================================================================
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// binary to grey conversion and grey to binary conversion for CDC circuitry
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// ==========================================================================
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function [7:0] b2g;
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input [7:0] b;
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reg [7:0] g;
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begin
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g[7] = b[7];
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g[6] = b[7] ^ b[6];
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g[5] = b[6] ^ b[5];
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g[4] = b[5] ^ b[4];
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g[3] = b[4] ^ b[3];
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g[2] = b[3] ^ b[2];
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g[1] = b[2] ^ b[1];
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g[0] = b[1] ^ b[0];
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b2g = g;
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end
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endfunction
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function [7:0] g2b;
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input [7:0] g;
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reg [7:0] b;
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begin
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b[7] = g[7];
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b[6] = b[7] ^ g[6];
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b[5] = b[6] ^ g[5];
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b[4] = b[5] ^ g[4];
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b[3] = b[4] ^ g[3];
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b[2] = b[3] ^ g[2];
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b[1] = b[2] ^ g[1];
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b[0] = b[1] ^ g[0];
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g2b = b;
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end
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endfunction
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// ==========================================================================
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// An asymmetric memory to transfer data from Avalon interface to DAC
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// interface
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// ==========================================================================
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (AVL_MEM_ADDRESS_WIDTH),
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.A_DATA_WIDTH (AVL_DATA_WIDTH),
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.B_ADDRESS_WIDTH (DAC_MEM_ADDRESS_WIDTH),
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.B_DATA_WIDTH (DAC_DATA_WIDTH))
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i_mem_asym (
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.clka (avl_clk),
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.wea (avl_mem_wr_enable),
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.addra (avl_mem_wr_address),
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.dina (avl_mem_data),
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.clkb (dac_clk),
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.addrb (dac_mem_rd_address),
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.doutb (dac_mem_data_s));
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// ==========================================================================
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// Avalon Memory Mapped interface access
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// ==========================================================================
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// Avalon address generation and read control signaling
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_address <= AVL_DDR_BASE_ADDRESS;
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end else begin
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if (avl_readdatavalid == 1'b1) begin
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avl_address <= (avl_address < avl_last_address) ? avl_address + 1 : 0;
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end
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end
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end
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assign avl_read_en_s = avl_xfer_req & avl_mem_request_data;
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_read <= 1'b0;
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avl_read_inprogress <= 1'b0;
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end else begin
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if ((avl_read_inprogress == 1'b0) && (avl_read_en_s == 1'b1)) begin
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avl_read <= 1'b1;
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avl_read_inprogress <= 1'b1;
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end else if (avl_read_inprogress == 1'b1) begin
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avl_read <= 1'b0;
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if (avl_readdatavalid == 1'b1) begin
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avl_read_inprogress <= 1'b0;
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end
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end
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end
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end
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always @(posedge avl_clk) begin
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avl_burstcount <= 1'b1;
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avl_byteenable <= {64{1'b1}};
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end
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// write data from Avalon interface into the async FIFO
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assign avl_mem_wr_enable_s = avl_readdatavalid & avl_ready;
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_mem_data <= 0;
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avl_mem_wr_enable <= 0;
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end else begin
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avl_mem_wr_enable <= avl_mem_wr_enable_s;
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if (avl_mem_wr_enable_s == 1'b1) begin
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avl_mem_data <= avl_data;
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end
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end
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end
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always @(posedge avl_clk) begin
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avl_xfer_req_d <= avl_xfer_req;
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avl_xfer_req_dd <= avl_xfer_req_d;
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end
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assign avl_xfer_req_init_s = avl_xfer_req_d & ~avl_xfer_req_dd;
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always @(posedge avl_clk) begin
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if ((avl_reset == 1'b1) || (avl_xfer_req_init_s == 1'b1)) begin
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avl_mem_wr_address <= 0;
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avl_mem_wr_address_g <= 0;
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end else begin
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if (avl_mem_wr_enable == 1'b1) begin
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avl_mem_wr_address <= avl_mem_wr_address + 1;
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end
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avl_mem_wr_address_g <= b2g(avl_mem_wr_address);
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end
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end
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// ==========================================================================
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// control the FIFO to prevent overflow, underfloq is monitored
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// ==========================================================================
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assign avl_mem_rd_address_s = (MEM_RATIO == 1) ? avl_mem_rd_address :
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(MEM_RATIO == 2) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):1] :
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(MEM_RATIO == 4) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):2] :
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(MEM_RATIO == 8) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):3] :
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avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):4];
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assign avl_mem_address_diff_s = {1'b1, avl_mem_wr_address} - avl_mem_rd_address_s;
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always @(posedge avl_clk) begin
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if (avl_xfer_req == 1'b0) begin
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avl_mem_address_diff <= 'd0;
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avl_mem_rd_address <= 'd0;
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avl_mem_rd_address_m1 <= 'd0;
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avl_mem_rd_address_m2 <= 'd0;
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avl_mem_request_data <= 'd0;
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end else begin
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avl_mem_rd_address_m1 <= dac_mem_rd_address_g;
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avl_mem_rd_address_m2 <= avl_mem_rd_address_m1;
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avl_mem_rd_address <= g2b(avl_mem_rd_address_m2);
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avl_mem_address_diff <= avl_mem_address_diff_s[AVL_MEM_ADDRESS_WIDTH-1:0];
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if (avl_mem_address_diff >= AVL_MEM_THRESHOLD_HI) begin
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avl_mem_request_data <= 1'b0;
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end else if (avl_mem_address_diff <= AVL_MEM_THRESHOLD_LO) begin
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avl_mem_request_data <= 1'b1;
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end
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end
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end
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// ==========================================================================
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// Push data from the async FIFO to the DAC
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// Data flow is controlled by the DAC, no back-pressure. If FIFO is not
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// ready, data will be dropped
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// ==========================================================================
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assign dac_mem_wr_address_s = (MEM_RATIO == 1) ? dac_mem_wr_address :
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(MEM_RATIO == 2) ? {dac_mem_wr_address, 1'b0} :
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(MEM_RATIO == 4) ? {dac_mem_wr_address, 2'b0} :
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(MEM_RATIO == 8) ? {dac_mem_wr_address, 3'b0} :
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{dac_mem_wr_address, 4'b0};
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assign dac_mem_address_diff_s = {1'b1, dac_mem_wr_address_s} - dac_mem_rd_address;
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always @(posedge dac_clk) begin
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if (dac_reset == 1'b1) begin
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dac_mem_wr_address_m2 <= 0;
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dac_mem_wr_address_m1 <= 0;
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dac_mem_wr_address <= 0;
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end else begin
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dac_mem_wr_address_m1 <= avl_mem_wr_address_g;
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dac_mem_wr_address_m2 <= dac_mem_wr_address_m1;
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dac_mem_wr_address <= g2b(dac_mem_wr_address_m2);
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end
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end
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always @(posedge dac_clk) begin
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if (dac_reset == 1'b1) begin
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dac_avl_xfer_req_m2 <= 0;
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dac_avl_xfer_req_m1 <= 0;
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dac_avl_xfer_req <= 0;
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end else begin
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dac_avl_xfer_req_m1 <= avl_xfer_req;
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dac_avl_xfer_req_m2 <= dac_avl_xfer_req_m1;
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dac_avl_xfer_req <= dac_avl_xfer_req_m1;
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end
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end
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assign dac_mem_rd_enable_s = (dac_xfer_req == 1'b1) ? dac_valid : 0;
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always @(posedge dac_clk) begin
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if ((dac_reset == 1'b1) || ((dac_avl_xfer_req == 1'b0) && (dac_xfer_req == 1'b0))) begin
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dac_mem_rd_address <= 0;
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dac_mem_rd_address_g <= 0;
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dac_mem_address_diff <= 0;
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end else begin
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dac_mem_address_diff <= dac_mem_address_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0];
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if (dac_mem_rd_enable_s == 1'b1) begin
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dac_mem_rd_address <= dac_mem_rd_address + 1;
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end
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dac_mem_rd_address_g <= b2g(dac_mem_rd_address);
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end
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end
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always @(posedge dac_clk) begin
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if (dac_reset == 1'b1) begin
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dac_xfer_req <= 0;
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end else begin
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if ((dac_avl_xfer_req == 1'b1) && (dac_mem_address_diff > 0)) begin
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dac_xfer_req <= 1'b1;
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end else if ((dac_avl_xfer_req == 1'b0) && (dac_mem_address_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0] == 0)) begin
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dac_xfer_req <= 1'b0;
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end
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end
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end
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always @(posedge dac_clk) begin
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if ((dac_reset == 1'b1) || (dac_xfer_req == 1'b0)) begin
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dac_data <= 0;
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end else begin
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dac_data <= dac_mem_data_s;
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end
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end
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always @(posedge dac_clk) begin
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if ((dac_reset == 1'b1) || (dac_xfer_req == 1'b0)) begin
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dac_dunf <= 1'b0;
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end else begin
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dac_dunf <= (dac_mem_address_diff == 0) ? 1'b1 : 1'b0;
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end
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end
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endmodule
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