116 lines
3.9 KiB
Verilog
116 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_lvds_in #(
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parameter SINGLE_ENDED = 0,
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parameter DEVICE_TYPE = 0,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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// data interface
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input rx_clk,
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input rx_data_in_p,
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input rx_data_in_n,
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output reg rx_data_p,
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output reg rx_data_n,
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// delay-data interface
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// internal registers
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// internal signals
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wire rx_data_p_s;
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wire rx_data_n_s;
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// defaults
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assign up_drdata = 5'd0;
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assign delay_locked = 1'b1;
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// instantiations
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generate
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if (DEVICE_TYPE == 0) begin
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alt_ddio_in i_rx_data_iddr (
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.ck (rx_clk),
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.pad_in (rx_data_in_p),
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.dout ({rx_data_p_s, rx_data_n_s}));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == 1) begin
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altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
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.inclock (rx_clk),
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.datain (rx_data_in_p),
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.dataout_h (rx_data_p_s),
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.dataout_l (rx_data_n_s),
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.inclocken (1'b1),
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.aclr (1'b0),
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.aset (1'b0),
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.sclr (1'b0),
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.sset (1'b0));
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end
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endgenerate
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always @(posedge rx_clk) begin
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rx_data_p <= rx_data_p_s;
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rx_data_n <= rx_data_n_s;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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