194 lines
6.2 KiB
Verilog
194 lines
6.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This is the dac physical interface (drives samples from the low speed clock to the
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// dac clock domain.
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`timescale 1ns/100ps
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module axi_ad9739a_if #(
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parameter DEVICE_TYPE = 0) (
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// dac interface
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input dac_clk_in_p,
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input dac_clk_in_n,
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output dac_clk_out_p,
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output dac_clk_out_n,
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output [13:0] dac_data_out_a_p,
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output [13:0] dac_data_out_a_n,
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output [13:0] dac_data_out_b_p,
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output [13:0] dac_data_out_b_n,
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// internal resets and clocks
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input dac_rst,
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output dac_clk,
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output dac_div_clk,
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output reg dac_status,
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// data interface
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input [15:0] dac_data_00,
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input [15:0] dac_data_01,
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input [15:0] dac_data_02,
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input [15:0] dac_data_03,
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input [15:0] dac_data_04,
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input [15:0] dac_data_05,
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input [15:0] dac_data_06,
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input [15:0] dac_data_07,
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input [15:0] dac_data_08,
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input [15:0] dac_data_09,
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input [15:0] dac_data_10,
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input [15:0] dac_data_11,
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input [15:0] dac_data_12,
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input [15:0] dac_data_13,
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input [15:0] dac_data_14,
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input [15:0] dac_data_15);
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// internal registers
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// internal signals
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wire dac_clk_in_s;
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wire dac_div_clk_s;
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// dac status
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always @(posedge dac_div_clk) begin
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if (dac_rst == 1'b1) begin
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dac_status <= 1'd0;
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end else begin
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dac_status <= 1'd1;
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end
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end
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// dac data output serdes(s) & buffers
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ad_serdes_out #(
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.DDR_OR_SDR_N(1),
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.DATA_WIDTH(14),
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.DEVICE_TYPE (DEVICE_TYPE))
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i_serdes_out_data_a (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.loaden (1'b0),
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.data_s0 (dac_data_00[15:2]),
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.data_s1 (dac_data_02[15:2]),
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.data_s2 (dac_data_04[15:2]),
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.data_s3 (dac_data_06[15:2]),
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.data_s4 (dac_data_08[15:2]),
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.data_s5 (dac_data_10[15:2]),
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.data_s6 (dac_data_12[15:2]),
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.data_s7 (dac_data_14[15:2]),
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.data_out_p (dac_data_out_a_p),
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.data_out_n (dac_data_out_a_n));
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// dac data output serdes(s) & buffers
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ad_serdes_out #(
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.DDR_OR_SDR_N(1),
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.DATA_WIDTH(14),
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.DEVICE_TYPE (DEVICE_TYPE))
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i_serdes_out_data_b (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.loaden (1'b0),
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.data_s0 (dac_data_01[15:2]),
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.data_s1 (dac_data_03[15:2]),
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.data_s2 (dac_data_05[15:2]),
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.data_s3 (dac_data_07[15:2]),
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.data_s4 (dac_data_09[15:2]),
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.data_s5 (dac_data_11[15:2]),
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.data_s6 (dac_data_13[15:2]),
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.data_s7 (dac_data_15[15:2]),
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.data_out_p (dac_data_out_b_p),
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.data_out_n (dac_data_out_b_n));
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// dac clock output serdes & buffer
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ad_serdes_out #(
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.DDR_OR_SDR_N(1),
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.DATA_WIDTH(1),
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.DEVICE_TYPE (DEVICE_TYPE))
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i_serdes_out_clk (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.loaden (1'b0),
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.data_s0 (1'b1),
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.data_s1 (1'b0),
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.data_s2 (1'b1),
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.data_s3 (1'b0),
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.data_s4 (1'b1),
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.data_s5 (1'b0),
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.data_s6 (1'b1),
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.data_s7 (1'b0),
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.data_out_p (dac_clk_out_p),
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.data_out_n (dac_clk_out_n));
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// dac clock input buffers
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IBUFGDS i_dac_clk_in_ibuf (
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.I (dac_clk_in_p),
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.IB (dac_clk_in_n),
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.O (dac_clk_in_s));
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BUFG i_dac_clk_in_gbuf (
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.I (dac_clk_in_s),
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.O (dac_clk));
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BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (dac_clk_in_s),
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.O (dac_div_clk_s));
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BUFG i_dac_div_clk_gbuf (
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.I (dac_div_clk_s),
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.O (dac_div_clk));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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