483 lines
14 KiB
VHDL
483 lines
14 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- In this HDL repository, there are many different and unique modules, consisting
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-- of various HDL (Verilog or VHDL) components. The individual modules are
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-- developed independently, and may be accompanied by separate and unique license
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-- terms.
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--
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-- The user should read each of these license terms, and understand the
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-- freedoms and responsibilities that he or she has by using this source/core.
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--
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-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
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-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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-- A PARTICULAR PURPOSE.
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--
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-- Redistribution and use of source or resulting binaries, with or without modification
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-- of this file, are permitted under one of the following two license terms:
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory
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-- of this repository (LICENSE_GPL2), and also online at:
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-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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--
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-- OR
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--
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-- 2. An ADI specific BSD license, which can be found in the top level directory
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-- of this repository (LICENSE_ADIBSD), and also on-line at:
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-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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-- This will allow to generate bit files and not release the source code,
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-- as long as it attaches to an ADI device.
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library work;
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use work.i2s_controller;
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library work;
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use work.axi_streaming_dma_rx_fifo;
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use work.axi_streaming_dma_tx_fifo;
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use work.pl330_dma_fifo;
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use work.axi_ctrlif;
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entity axi_i2s_adi is
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generic
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(
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-- ADD USER GENERICS BELOW THIS LINE ---------------
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SLOT_WIDTH : integer := 24;
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LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
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BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol parameters, do not add to or delete
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S_AXI_DATA_WIDTH : integer := 32;
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S_AXI_ADDRESS_WIDTH : integer := 32;
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DEVICE_FAMILY : string := "virtex6";
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-- DO NOT EDIT ABOVE THIS LINE ---------------------
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DMA_TYPE : integer := 0;
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NUM_OF_CHANNEL : integer := 1;
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HAS_TX : integer := 1;
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HAS_RX : integer := 1
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);
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port
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(
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-- Serial Data interface
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data_clk_i : in std_logic;
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bclk_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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lrclk_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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sdata_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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sdata_i : in std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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-- AXI Streaming DMA TX interface
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s_axis_aclk : in std_logic;
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s_axis_aresetn : in std_logic;
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s_axis_tready : out std_logic;
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s_axis_tdata : in std_logic_vector(31 downto 0);
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s_axis_tlast : in std_logic;
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s_axis_tvalid : in std_logic;
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-- AXI Streaming DMA RX interface
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m_axis_aclk : in std_logic;
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m_axis_tready : in std_logic;
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m_axis_tdata : out std_logic_vector(31 downto 0);
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m_axis_tlast : out std_logic;
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m_axis_tvalid : out std_logic;
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m_axis_tkeep : out std_logic_vector(3 downto 0);
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--PL330 DMA TX interface
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dma_req_tx_aclk : in std_logic;
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dma_req_tx_rstn : in std_logic;
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dma_req_tx_davalid : in std_logic;
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dma_req_tx_datype : in std_logic_vector(1 downto 0);
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dma_req_tx_daready : out std_logic;
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dma_req_tx_drvalid : out std_logic;
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dma_req_tx_drtype : out std_logic_vector(1 downto 0);
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dma_req_tx_drlast : out std_logic;
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dma_req_tx_drready : in std_logic;
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-- PL330 DMA RX interface
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dma_req_rx_aclk : in std_logic;
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dma_req_rx_rstn : in std_logic;
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dma_req_rx_davalid : in std_logic;
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dma_req_rx_datype : in std_logic_vector(1 downto 0);
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dma_req_rx_daready : out std_logic;
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dma_req_rx_drvalid : out std_logic;
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dma_req_rx_drtype : out std_logic_vector(1 downto 0);
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dma_req_rx_drlast : out std_logic;
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dma_req_rx_drready : in std_logic;
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-- AXI bus interface
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s_axi_aclk : in std_logic;
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s_axi_aresetn : in std_logic;
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s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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s_axi_awvalid : in std_logic;
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s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
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s_axi_wvalid : in std_logic;
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s_axi_bready : in std_logic;
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s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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s_axi_arvalid : in std_logic;
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s_axi_rready : in std_logic;
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s_axi_arready : out std_logic;
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s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_rresp : out std_logic_vector(1 downto 0);
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s_axi_rvalid : out std_logic;
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s_axi_wready : out std_logic;
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s_axi_bresp : out std_logic_vector(1 downto 0);
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s_axi_bvalid : out std_logic;
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s_axi_awready : out std_logic;
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s_axi_awprot : in std_logic_vector(2 downto 0);
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s_axi_arprot : in std_logic_vector(2 downto 0)
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);
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end entity axi_i2s_adi;
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architecture Behavioral of axi_i2s_adi is
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------------------------------------------
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-- Signals for user logic slave model s/w accessible register example
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------------------------------------------
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signal i2s_reset : std_logic;
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signal tx_fifo_reset : std_logic;
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signal tx_enable : Boolean;
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signal tx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
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signal tx_ack : std_logic;
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signal tx_stb : std_logic;
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signal rx_enable : Boolean;
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signal rx_fifo_reset : std_logic;
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signal rx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
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signal rx_ack : std_logic;
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signal rx_stb : std_logic;
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signal const_1 : std_logic;
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signal bclk_div_rate : natural range 0 to 255;
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signal lrclk_div_rate : natural range 0 to 255;
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signal period_len : integer range 0 to 65535;
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signal I2S_RESET_REG : std_logic_vector(31 downto 0);
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signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
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signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
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signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
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constant FIFO_AWIDTH : integer := integer(ceil(log2(real(NUM_OF_CHANNEL * 8))));
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-- Audio samples FIFO
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constant RAM_ADDR_WIDTH : integer := 7;
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type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
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-- RX FIFO signals
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signal audio_fifo_rx : RAM_TYPE;
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signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
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signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
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signal tvalid : std_logic := '0';
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signal rx_tlast : std_logic;
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signal drain_tx_dma : std_logic;
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signal rx_sample : std_logic_vector(23 downto 0);
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signal wr_data : std_logic_vector(31 downto 0);
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signal rd_data : std_logic_vector(31 downto 0);
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signal wr_addr : integer range 0 to 11;
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signal rd_addr : integer range 0 to 11;
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signal wr_stb : std_logic;
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signal rd_ack : std_logic;
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signal tx_fifo_stb : std_logic;
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signal rx_fifo_ack : std_logic;
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signal cnt : integer range 0 to 2**16-1;
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begin
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const_1 <= '1';
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process (s_axi_aclk)
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begin
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if rising_edge(s_axi_aclk) then
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if s_axi_aresetn = '0' then
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cnt <= 0;
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else
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cnt <= (cnt + 1) mod 2**16;
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end if;
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end if;
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end process;
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streaming_dma_tx_gen: if DMA_TYPE = 0 and HAS_TX = 1 generate
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tx_fifo : entity axi_streaming_dma_tx_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24
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)
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port map(
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => tx_fifo_reset,
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enable => tx_enable,
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s_axis_aclk => s_axis_aclk,
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s_axis_tready => s_axis_tready,
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s_axis_tdata => s_axis_tdata(31 downto 8),
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s_axis_tlast => s_axis_tlast,
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s_axis_tvalid => s_axis_tvalid,
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out_stb => tx_stb,
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out_ack => tx_ack,
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out_data => tx_data
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);
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end generate;
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no_streaming_dma_tx_gen: if DMA_TYPE /= 0 or HAS_TX /= 1 generate
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s_axis_tready <= '0';
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end generate;
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streaming_dma_rx_gen: if DMA_TYPE = 0 and HAS_RX = 1 generate
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rx_fifo : entity axi_streaming_dma_rx_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24
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)
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port map(
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => tx_fifo_reset,
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enable => tx_enable,
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period_len => period_len,
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in_stb => rx_stb,
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in_ack => rx_ack,
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in_data => rx_data,
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m_axis_aclk => m_axis_aclk,
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m_axis_tready => m_axis_tready,
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m_axis_tdata => m_axis_tdata(31 downto 8),
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m_axis_tlast => m_axis_tlast,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tkeep => m_axis_tkeep
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);
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m_axis_tdata(7 downto 0) <= (others => '0');
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end generate;
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no_streaming_dma_rx_gen: if DMA_TYPE /= 0 or HAS_RX /= 1 generate
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m_axis_tdata <= (others => '0');
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m_axis_tlast <= '0';
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m_axis_tvalid <= '0';
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m_axis_tkeep <= (others => '0');
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end generate;
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pl330_dma_tx_gen: if DMA_TYPE = 1 and HAS_TX = 1 generate
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tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
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tx_fifo: entity pl330_dma_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24,
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FIFO_DIRECTION => 0
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => tx_fifo_reset,
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enable => tx_enable,
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in_data => wr_data(31 downto 8),
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in_stb => tx_fifo_stb,
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out_ack => tx_ack,
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out_stb => tx_stb,
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out_data => tx_data,
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dclk => dma_req_tx_aclk,
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dresetn => dma_req_tx_rstn,
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davalid => dma_req_tx_davalid,
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daready => dma_req_tx_daready,
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datype => dma_req_tx_datype,
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drvalid => dma_req_tx_drvalid,
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drready => dma_req_tx_drready,
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drtype => dma_req_tx_drtype,
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drlast => dma_req_tx_drlast
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);
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end generate;
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no_pl330_dma_tx_gen: if DMA_TYPE /= 1 or HAS_TX /= 1 generate
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dma_req_tx_daready <= '0';
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dma_req_tx_drvalid <= '0';
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dma_req_tx_drtype <= (others => '0');
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dma_req_tx_drlast <= '0';
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end generate;
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pl330_dma_rx_gen: if DMA_TYPE = 1 and HAS_RX = 1 generate
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rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
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rx_fifo: entity pl330_dma_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24,
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FIFO_DIRECTION => 1
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => rx_fifo_reset,
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enable => rx_enable,
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in_ack => rx_ack,
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in_stb => rx_stb,
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in_data => rx_data,
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out_data => rx_sample,
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out_ack => rx_fifo_ack,
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dclk => dma_req_rx_aclk,
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dresetn => dma_req_rx_rstn,
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davalid => dma_req_rx_davalid,
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daready => dma_req_rx_daready,
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datype => dma_req_rx_datype,
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drvalid => dma_req_rx_drvalid,
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drready => dma_req_rx_drready,
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drtype => dma_req_rx_drtype,
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drlast => dma_req_rx_drlast
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);
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end generate;
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no_pl330_dma_rx_gen: if DMA_TYPE /= 1 or HAS_RX /= 1 generate
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dma_req_rx_daready <= '0';
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dma_req_rx_drvalid <= '0';
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dma_req_rx_drtype <= (others => '0');
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dma_req_rx_drlast <= '0';
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end generate;
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ctrl : entity i2s_controller
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generic map (
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C_SLOT_WIDTH => SLOT_WIDTH,
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C_BCLK_POL => BCLK_POL,
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C_LRCLK_POL => LRCLK_POL,
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C_NUM_CH => NUM_OF_CHANNEL,
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C_HAS_TX => HAS_TX,
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C_HAS_RX => HAS_RX
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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data_clk => data_clk_i,
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bclk_o => bclk_o,
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lrclk_o => lrclk_o,
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sdata_o => sdata_o,
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sdata_i => sdata_i,
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tx_enable => tx_enable,
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tx_ack => tx_ack,
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tx_stb => tx_stb,
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tx_data => tx_data,
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rx_enable => rx_enable,
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rx_ack => rx_ack,
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rx_stb => rx_stb,
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rx_data => rx_data,
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bclk_div_rate => bclk_div_rate,
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lrclk_div_rate => lrclk_div_rate
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);
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i2s_reset <= I2S_RESET_REG(0);
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tx_fifo_reset <= I2S_RESET_REG(1);
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rx_fifo_reset <= I2S_RESET_REG(2);
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tx_enable <= I2S_CONTROL_REG(0) = '1';
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rx_enable <= I2S_CONTROL_REG(1) = '1';
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bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
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lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
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period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
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ctrlif: entity axi_ctrlif
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generic map (
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C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
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C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
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C_NUM_REG => 12
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)
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port map(
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s_axi_aclk => s_axi_aclk,
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s_axi_aresetn => s_axi_aresetn,
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s_axi_awaddr => s_axi_awaddr,
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s_axi_awvalid => s_axi_awvalid,
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s_axi_wdata => s_axi_wdata,
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s_axi_wstrb => s_axi_wstrb,
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s_axi_wvalid => s_axi_wvalid,
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s_axi_bready => s_axi_bready,
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s_axi_araddr => s_axi_araddr,
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s_axi_arvalid => s_axi_arvalid,
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s_axi_rready => s_axi_rready,
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s_axi_arready => s_axi_arready,
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s_axi_rdata => s_axi_rdata,
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s_axi_rresp => s_axi_rresp,
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s_axi_rvalid => s_axi_rvalid,
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s_axi_wready => s_axi_wready,
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s_axi_bresp => s_axi_bresp,
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s_axi_bvalid => s_axi_bvalid,
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s_axi_awready => s_axi_awready,
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rd_addr => rd_addr,
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rd_data => rd_data,
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rd_ack => rd_ack,
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rd_stb => const_1,
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wr_addr => wr_addr,
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wr_data => wr_data,
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wr_ack => const_1,
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wr_stb => wr_stb
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);
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process(rd_addr, I2S_CONTROL_REG, I2S_CLK_CONTROL_REG, PERIOD_LEN_REG, rx_sample, cnt)
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begin
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case rd_addr is
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when 1 => rd_data <= I2S_CONTROL_REG and x"00000003";
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when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
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when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
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when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
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when others => rd_data <= (others => '0');
|
|
end case;
|
|
end process;
|
|
|
|
process(s_axi_aclk) is
|
|
begin
|
|
if rising_edge(s_axi_aclk) then
|
|
if s_axi_aresetn = '0' then
|
|
I2S_RESET_REG <= (others => '0');
|
|
I2S_CONTROL_REG <= (others => '0');
|
|
I2S_CLK_CONTROL_REG <= (others => '0');
|
|
PERIOD_LEN_REG <= (others => '0');
|
|
else
|
|
-- Auto-clear the Reset Register bits
|
|
I2S_RESET_REG(0) <= '0';
|
|
I2S_RESET_REG(1) <= '0';
|
|
I2S_RESET_REG(2) <= '0';
|
|
if wr_stb = '1' then
|
|
case wr_addr is
|
|
when 0 => I2S_RESET_REG <= wr_data;
|
|
when 1 => I2S_CONTROL_REG <= wr_data;
|
|
when 2 => I2S_CLK_CONTROL_REG <= wr_data;
|
|
when 6 => PERIOD_LEN_REG <= wr_data;
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end Behavioral;
|