4b13274c55
Having a clock assigned manually to the clk output pin of the axi_ad9361 let the Vivado timing engine to not ignore the clock insertion delay when analyzing paths between clk_0 and the manually created clock that has the same source (clk_0), resulting in timing failure. |
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| .. | ||
| adrv9364z7020_bd.tcl | ||
| adrv9364z7020_constr.xdc | ||
| adrv9364z7020_constr_cmos.xdc | ||
| adrv9364z7020_constr_lvds.xdc | ||
| ccbob_bd.tcl | ||
| ccbob_constr.xdc | ||
| ccbox_bd.tcl | ||
| ccbox_constr.xdc | ||