712 lines
25 KiB
Verilog
712 lines
25 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_jesd_gt (
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// physical interface
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ref_clk_q,
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ref_clk_c,
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rx_data_p,
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rx_data_n,
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rx_sync,
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rx_sysref,
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rx_ext_sysref,
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tx_data_p,
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tx_data_n,
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tx_sync,
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tx_sysref,
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tx_ext_sysref,
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// core interface
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rx_rst,
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rx_clk_g,
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rx_clk,
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rx_data,
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rx_gt_charisk,
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rx_gt_disperr,
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rx_gt_notintable,
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rx_gt_data,
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rx_rst_done,
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rx_ip_comma_align,
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rx_ip_sync,
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rx_ip_sof,
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rx_ip_data,
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tx_rst,
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tx_clk_g,
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tx_clk,
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tx_data,
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tx_gt_charisk,
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tx_gt_data,
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tx_rst_done,
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tx_ip_sync,
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tx_ip_sof,
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tx_ip_data,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rready,
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// master interface
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m_axi_aclk,
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m_axi_aresetn,
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m_axi_awvalid,
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m_axi_awaddr,
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m_axi_awprot,
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m_axi_awready,
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m_axi_wvalid,
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m_axi_wdata,
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m_axi_wstrb,
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m_axi_wready,
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m_axi_bvalid,
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m_axi_bresp,
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m_axi_bready,
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m_axi_arvalid,
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m_axi_araddr,
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m_axi_arprot,
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m_axi_arready,
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m_axi_rvalid,
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m_axi_rdata,
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m_axi_rresp,
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m_axi_rready,
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// drp clock
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drp_clk,
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// es debug interface
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es_dbg_data,
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es_dbg_trigger,
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// jesd debug interface
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rx_mon_data,
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rx_mon_trigger,
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tx_mon_data,
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tx_mon_trigger);
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parameter PCORE_ID = 0;
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_NUM_OF_LANES = 4;
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parameter PCORE_QPLL_REFCLK_DIV = 1;
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parameter PCORE_QPLL_CFG = 27'h0680181;
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parameter PCORE_QPLL_FBDIV_RATIO = 1'b1;
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parameter PCORE_QPLL_FBDIV = 10'b0000110000;
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parameter PCORE_CPLL_FBDIV = 2;
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parameter PCORE_RX_OUT_DIV = 1;
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parameter PCORE_TX_OUT_DIV = 1;
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parameter PCORE_RX_CLK25_DIV = 20;
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parameter PCORE_TX_CLK25_DIV = 20;
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parameter PCORE_PMA_RSV = 32'h001E7080;
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parameter PCORE_RX_CDR_CFG = 72'h0b000023ff10400020;
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parameter C_S_AXI_MIN_SIZE = 32'hffff;
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parameter C_BASEADDR = 32'h00000000;
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parameter C_HIGHADDR = 32'hffffffff;
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// physical interface
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input ref_clk_q;
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input ref_clk_c;
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input [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_p;
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input [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_n;
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output rx_sync;
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output rx_sysref;
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input rx_ext_sysref;
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output [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_p;
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output [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_n;
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input tx_sync;
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output tx_sysref;
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input tx_ext_sysref;
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// core interface
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output rx_rst;
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output rx_clk_g;
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input rx_clk;
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output [((PCORE_NUM_OF_LANES*32)-1):0] rx_data;
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output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_charisk;
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output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr;
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output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable;
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output [((PCORE_NUM_OF_LANES*32)-1):0] rx_gt_data;
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output rx_rst_done;
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input rx_ip_comma_align;
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input rx_ip_sync;
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input [ 3:0] rx_ip_sof;
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input [((PCORE_NUM_OF_LANES*32)-1):0] rx_ip_data;
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output tx_rst;
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output tx_clk_g;
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input tx_clk;
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input [((PCORE_NUM_OF_LANES*32)-1):0] tx_data;
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input [((PCORE_NUM_OF_LANES* 4)-1):0] tx_gt_charisk;
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input [((PCORE_NUM_OF_LANES*32)-1):0] tx_gt_data;
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output tx_rst_done;
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output tx_ip_sync;
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input [ 3:0] tx_ip_sof;
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output [((PCORE_NUM_OF_LANES*32)-1):0] tx_ip_data;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [ 31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [ 31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [ 31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 31:0] s_axi_rdata;
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output [ 1:0] s_axi_rresp;
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input s_axi_rready;
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// master interface
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input m_axi_aclk;
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input m_axi_aresetn;
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output m_axi_awvalid;
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output [ 31:0] m_axi_awaddr;
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output [ 2:0] m_axi_awprot;
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input m_axi_awready;
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output m_axi_wvalid;
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output [ 31:0] m_axi_wdata;
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output [ 3:0] m_axi_wstrb;
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input m_axi_wready;
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input m_axi_bvalid;
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input [ 1:0] m_axi_bresp;
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output m_axi_bready;
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output m_axi_arvalid;
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output [ 31:0] m_axi_araddr;
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output [ 2:0] m_axi_arprot;
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input m_axi_arready;
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input m_axi_rvalid;
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input [ 31:0] m_axi_rdata;
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input [ 1:0] m_axi_rresp;
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output m_axi_rready;
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// drp clock
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input drp_clk;
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// es debug interface
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output [275:0] es_dbg_data;
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output [ 7:0] es_dbg_trigger;
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// jesd debug interface
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output [((PCORE_NUM_OF_LANES*82)+5):0] rx_mon_data;
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output [((PCORE_NUM_OF_LANES* 1)+1):0] rx_mon_trigger;
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output [((PCORE_NUM_OF_LANES*36)+5):0] tx_mon_data;
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output [ 5:0] tx_mon_trigger;
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// reset and clocks
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wire gt_pll_rst;
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wire gt_rx_rst;
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wire gt_tx_rst;
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wire qpll_clk_0;
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wire qpll_ref_clk_0;
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wire qpll_clk_1;
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wire qpll_ref_clk_1;
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wire [ 7:0] qpll_clk;
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wire [ 7:0] qpll_ref_clk;
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wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_out_clk;
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wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_out_clk;
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wire axi_rstn;
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wire axi_clk;
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wire up_rstn;
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wire up_clk;
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wire drp_rst;
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// internal signals
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wire [ 8:0] up_status_extn_s;
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wire [ 8:0] rx_rst_done_extn_s;
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wire [ 8:0] rx_pll_locked_extn_s;
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wire [ 8:0] tx_rst_done_extn_s;
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wire [ 8:0] tx_pll_locked_extn_s;
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wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_mon_trigger_s;
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wire [((PCORE_NUM_OF_LANES*50)-1):0] rx_mon_data_s;
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wire [ 15:0] drp_rdata_gt_s[15:0];
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wire drp_ready_gt_s[15:0];
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wire [ 7:0] drp_rx_rate_gt_s[15:0];
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wire qpll_locked_0_s;
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wire qpll_locked_1_s;
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wire [ 7:0] qpll_locked_s;
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wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_rst_done_s;
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wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_pll_locked_s;
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wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_rst_done_s;
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wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_pll_locked_s;
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wire up_cpll_pd_s;
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wire [ 1:0] up_rx_sys_clk_sel_s;
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wire [ 2:0] up_rx_out_clk_sel_s;
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wire [ 1:0] up_tx_sys_clk_sel_s;
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wire [ 2:0] up_tx_out_clk_sel_s;
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wire drp_sel_s;
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wire drp_wr_s;
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wire [ 11:0] drp_addr_s;
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wire [ 15:0] drp_wdata_s;
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wire [ 15:0] drp_rdata_s;
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wire drp_ready_s;
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wire [ 7:0] drp_lanesel_s;
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wire [ 7:0] drp_rx_rate_s;
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wire es_sel_s;
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wire es_wr_s;
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wire [ 11:0] es_addr_s;
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wire [ 15:0] es_wdata_s;
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wire [ 15:0] es_rdata_s;
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wire es_ready_s;
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wire es_start_s;
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wire es_stop_s;
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wire es_init_s;
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wire [ 15:0] es_sdata0_s;
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wire [ 15:0] es_sdata1_s;
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wire [ 15:0] es_sdata2_s;
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wire [ 15:0] es_sdata3_s;
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wire [ 15:0] es_sdata4_s;
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wire [ 15:0] es_qdata0_s;
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wire [ 15:0] es_qdata1_s;
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wire [ 15:0] es_qdata2_s;
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wire [ 15:0] es_qdata3_s;
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wire [ 15:0] es_qdata4_s;
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wire [ 4:0] es_prescale_s;
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wire [ 11:0] es_hoffset_min_s;
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wire [ 11:0] es_hoffset_max_s;
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wire [ 11:0] es_hoffset_step_s;
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wire [ 7:0] es_voffset_min_s;
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wire [ 7:0] es_voffset_max_s;
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wire [ 7:0] es_voffset_step_s;
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wire [ 31:0] es_start_addr_s;
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wire es_dmaerr_s;
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wire es_status_s;
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wire up_sel_s;
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wire up_wr_s;
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wire [ 13:0] up_addr_s;
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wire [ 31:0] up_wdata_s;
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wire [ 31:0] up_rdata_s;
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wire up_ack_s;
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// debug interface
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assign rx_mon_data = {rx_sync, rx_sysref, rx_ip_sof, rx_ip_data, rx_mon_data_s};
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assign rx_mon_trigger = {rx_sync, rx_sysref, rx_mon_trigger_s};
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assign tx_mon_data = {tx_sync, tx_sysref, tx_ip_sof, tx_gt_charisk, tx_gt_data};
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assign tx_mon_trigger = {tx_sync, tx_sysref, tx_ip_sof};
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// signal name changes
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assign axi_rstn = m_axi_aresetn;
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assign axi_clk = m_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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// drp is simply over-defined to avoid errors with singluar entries
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assign up_status_extn_s = 9'hff;
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assign rx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], rx_rst_done_s};
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assign rx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], rx_pll_locked_s};
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assign tx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_rst_done_s};
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assign tx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_pll_locked_s};
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assign rx_rst_done = | rx_rst_done_s;
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assign tx_rst_done = | tx_rst_done_s;
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assign drp_rdata_s = drp_rdata_gt_s[15] | drp_rdata_gt_s[14] |
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drp_rdata_gt_s[13] | drp_rdata_gt_s[12] |
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drp_rdata_gt_s[11] | drp_rdata_gt_s[10] |
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drp_rdata_gt_s[ 9] | drp_rdata_gt_s[ 8] |
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drp_rdata_gt_s[ 7] | drp_rdata_gt_s[ 6] |
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drp_rdata_gt_s[ 5] | drp_rdata_gt_s[ 4] |
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drp_rdata_gt_s[ 3] | drp_rdata_gt_s[ 2] |
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drp_rdata_gt_s[ 1] | drp_rdata_gt_s[ 0];
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assign drp_ready_s = drp_ready_gt_s[15] | drp_ready_gt_s[14] |
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drp_ready_gt_s[13] | drp_ready_gt_s[12] |
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drp_ready_gt_s[11] | drp_ready_gt_s[10] |
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drp_ready_gt_s[ 9] | drp_ready_gt_s[ 8] |
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drp_ready_gt_s[ 7] | drp_ready_gt_s[ 6] |
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drp_ready_gt_s[ 5] | drp_ready_gt_s[ 4] |
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drp_ready_gt_s[ 3] | drp_ready_gt_s[ 2] |
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drp_ready_gt_s[ 1] | drp_ready_gt_s[ 0];
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assign drp_rx_rate_s = drp_rx_rate_gt_s[15] | drp_rx_rate_gt_s[14] |
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drp_rx_rate_gt_s[13] | drp_rx_rate_gt_s[12] |
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drp_rx_rate_gt_s[11] | drp_rx_rate_gt_s[10] |
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drp_rx_rate_gt_s[ 9] | drp_rx_rate_gt_s[ 8] |
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drp_rx_rate_gt_s[ 7] | drp_rx_rate_gt_s[ 6] |
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drp_rx_rate_gt_s[ 5] | drp_rx_rate_gt_s[ 4] |
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drp_rx_rate_gt_s[ 3] | drp_rx_rate_gt_s[ 2] |
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drp_rx_rate_gt_s[ 1] | drp_rx_rate_gt_s[ 0];
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assign tx_ip_data = tx_data;
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// clock buffers
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BUFG i_bufg_rx_clk (
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.I (rx_out_clk[0]),
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.O (rx_clk_g));
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BUFG i_bufg_tx_clk (
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.I (tx_out_clk[0]),
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.O (tx_clk_g));
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// transceivers
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assign qpll_clk = {{4{qpll_clk_1}}, {4{qpll_clk_0}}};
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assign qpll_ref_clk = {{4{qpll_ref_clk_1}}, {4{qpll_ref_clk_0}}};
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assign qpll_locked_s = {{4{qpll_locked_1_s}}, {4{qpll_locked_0_s}}};
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ad_gt_common_1 #(
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.DRP_ID (14),
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.QPLL_REFCLK_DIV (PCORE_QPLL_REFCLK_DIV),
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.QPLL_CFG (PCORE_QPLL_CFG),
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.QPLL_FBDIV_RATIO (PCORE_QPLL_FBDIV_RATIO),
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.QPLL_FBDIV (PCORE_QPLL_FBDIV))
|
|
i_gt_common_1 (
|
|
.rst (gt_pll_rst),
|
|
.ref_clk (ref_clk_q),
|
|
.qpll_clk (qpll_clk_0),
|
|
.qpll_ref_clk (qpll_ref_clk_0),
|
|
.qpll_locked (qpll_locked_0_s),
|
|
.drp_clk (drp_clk),
|
|
.drp_sel (drp_sel_s),
|
|
.drp_addr (drp_addr_s),
|
|
.drp_wr (drp_wr_s),
|
|
.drp_wdata (drp_wdata_s),
|
|
.drp_rdata (drp_rdata_gt_s[14]),
|
|
.drp_ready (drp_ready_gt_s[14]),
|
|
.drp_lanesel (drp_lanesel_s),
|
|
.drp_rx_rate (drp_rx_rate_gt_s[14]));
|
|
|
|
ad_gt_common_1 #(
|
|
.DRP_ID (15),
|
|
.QPLL_REFCLK_DIV (PCORE_QPLL_REFCLK_DIV),
|
|
.QPLL_CFG (PCORE_QPLL_CFG),
|
|
.QPLL_FBDIV_RATIO (PCORE_QPLL_FBDIV_RATIO),
|
|
.QPLL_FBDIV (PCORE_QPLL_FBDIV))
|
|
i_gt_common_2 (
|
|
.rst (gt_pll_rst),
|
|
.ref_clk (ref_clk_q),
|
|
.qpll_clk (qpll_clk_1),
|
|
.qpll_ref_clk (qpll_ref_clk_1),
|
|
.qpll_locked (qpll_locked_1_s),
|
|
.drp_clk (drp_clk),
|
|
.drp_sel (drp_sel_s),
|
|
.drp_addr (drp_addr_s),
|
|
.drp_wr (drp_wr_s),
|
|
.drp_wdata (drp_wdata_s),
|
|
.drp_rdata (drp_rdata_gt_s[15]),
|
|
.drp_ready (drp_ready_gt_s[15]),
|
|
.drp_lanesel (drp_lanesel_s),
|
|
.drp_rx_rate (drp_rx_rate_gt_s[15]));
|
|
|
|
genvar n;
|
|
generate
|
|
for (n = 0; n < PCORE_NUM_OF_LANES; n = n + 1) begin: g_lane_1
|
|
|
|
ad_jesd_align i_jesd_align (
|
|
.rx_clk (rx_clk),
|
|
.rx_sof (rx_ip_sof),
|
|
.rx_ip_data (rx_ip_data[n*32+31:n*32]),
|
|
.rx_data (rx_data[n*32+31:n*32]));
|
|
|
|
ad_gt_channel_1 #(
|
|
.DRP_ID (n),
|
|
.CPLL_FBDIV (PCORE_CPLL_FBDIV),
|
|
.RX_OUT_DIV (PCORE_RX_OUT_DIV),
|
|
.TX_OUT_DIV (PCORE_TX_OUT_DIV),
|
|
.RX_CLK25_DIV (PCORE_RX_CLK25_DIV),
|
|
.TX_CLK25_DIV (PCORE_TX_CLK25_DIV),
|
|
.PMA_RSV (PCORE_PMA_RSV),
|
|
.RX_CDR_CFG (PCORE_RX_CDR_CFG))
|
|
i_gt_channel_1 (
|
|
.ref_clk (ref_clk_c),
|
|
.cpll_pd (up_cpll_pd_s),
|
|
.cpll_rst (gt_pll_rst),
|
|
.qpll_clk (qpll_clk[n]),
|
|
.qpll_ref_clk (qpll_ref_clk[n]),
|
|
.qpll_locked (qpll_locked_s[n]),
|
|
.rx_rst (gt_rx_rst),
|
|
.rx_p (rx_data_p[n]),
|
|
.rx_n (rx_data_n[n]),
|
|
.rx_sys_clk_sel (up_rx_sys_clk_sel_s),
|
|
.rx_out_clk_sel (up_rx_out_clk_sel_s),
|
|
.rx_out_clk (rx_out_clk[n]),
|
|
.rx_rst_done (rx_rst_done_s[n]),
|
|
.rx_pll_locked (rx_pll_locked_s[n]),
|
|
.rx_clk (rx_clk),
|
|
.rx_charisk (rx_gt_charisk[n*4+3:n*4]),
|
|
.rx_disperr (rx_gt_disperr[n*4+3:n*4]),
|
|
.rx_notintable (rx_gt_notintable[n*4+3:n*4]),
|
|
.rx_data (rx_gt_data[n*32+31:n*32]),
|
|
.rx_comma_align_enb (rx_ip_comma_align),
|
|
.tx_rst (gt_tx_rst),
|
|
.tx_p (tx_data_p[n]),
|
|
.tx_n (tx_data_n[n]),
|
|
.tx_sys_clk_sel (up_tx_sys_clk_sel_s),
|
|
.tx_out_clk_sel (up_tx_out_clk_sel_s),
|
|
.tx_out_clk (tx_out_clk[n]),
|
|
.tx_rst_done (tx_rst_done_s[n]),
|
|
.tx_pll_locked (tx_pll_locked_s[n]),
|
|
.tx_clk (tx_clk),
|
|
.tx_charisk (tx_gt_charisk[n*4+3:n*4]),
|
|
.tx_data (tx_gt_data[n*32+31:n*32]),
|
|
.drp_clk (drp_clk),
|
|
.drp_sel (drp_sel_s),
|
|
.drp_addr (drp_addr_s),
|
|
.drp_wr (drp_wr_s),
|
|
.drp_wdata (drp_wdata_s),
|
|
.drp_rdata (drp_rdata_gt_s[n]),
|
|
.drp_ready (drp_ready_gt_s[n]),
|
|
.drp_lanesel (drp_lanesel_s),
|
|
.drp_rx_rate (drp_rx_rate_gt_s[n]),
|
|
.rx_mon_trigger (rx_mon_trigger_s[n]),
|
|
.rx_mon_data (rx_mon_data_s[n*50+49:n*50]));
|
|
end
|
|
endgenerate
|
|
|
|
// eye scan
|
|
|
|
ad_gt_es #(.GTH_GTX_N(0)) i_gt_es (
|
|
.drp_rst (drp_rst),
|
|
.drp_clk (drp_clk),
|
|
.es_sel (es_sel_s),
|
|
.es_wr (es_wr_s),
|
|
.es_addr (es_addr_s),
|
|
.es_wdata (es_wdata_s),
|
|
.es_rdata (es_rdata_s),
|
|
.es_ready (es_ready_s),
|
|
.axi_rstn (axi_rstn),
|
|
.axi_clk (axi_clk),
|
|
.axi_awvalid (m_axi_awvalid),
|
|
.axi_awaddr (m_axi_awaddr),
|
|
.axi_awprot (m_axi_awprot),
|
|
.axi_awready (m_axi_awready),
|
|
.axi_wvalid (m_axi_wvalid),
|
|
.axi_wdata (m_axi_wdata),
|
|
.axi_wstrb (m_axi_wstrb),
|
|
.axi_wready (m_axi_wready),
|
|
.axi_bvalid (m_axi_bvalid),
|
|
.axi_bresp (m_axi_bresp),
|
|
.axi_bready (m_axi_bready),
|
|
.axi_arvalid (m_axi_arvalid),
|
|
.axi_araddr (m_axi_araddr),
|
|
.axi_arprot (m_axi_arprot),
|
|
.axi_arready (m_axi_arready),
|
|
.axi_rvalid (m_axi_rvalid),
|
|
.axi_rdata (m_axi_rdata),
|
|
.axi_rresp (m_axi_rresp),
|
|
.axi_rready (m_axi_rready),
|
|
.es_start (es_start_s),
|
|
.es_stop (es_stop_s),
|
|
.es_init (es_init_s),
|
|
.es_sdata0 (es_sdata0_s),
|
|
.es_sdata1 (es_sdata1_s),
|
|
.es_sdata2 (es_sdata2_s),
|
|
.es_sdata3 (es_sdata3_s),
|
|
.es_sdata4 (es_sdata4_s),
|
|
.es_qdata0 (es_qdata0_s),
|
|
.es_qdata1 (es_qdata1_s),
|
|
.es_qdata2 (es_qdata2_s),
|
|
.es_qdata3 (es_qdata3_s),
|
|
.es_qdata4 (es_qdata4_s),
|
|
.es_prescale (es_prescale_s),
|
|
.es_hoffset_min (es_hoffset_min_s),
|
|
.es_hoffset_max (es_hoffset_max_s),
|
|
.es_hoffset_step (es_hoffset_step_s),
|
|
.es_voffset_min (es_voffset_min_s),
|
|
.es_voffset_max (es_voffset_max_s),
|
|
.es_voffset_step (es_voffset_step_s),
|
|
.es_start_addr (es_start_addr_s),
|
|
.es_dmaerr (es_dmaerr_s),
|
|
.es_status (es_status_s),
|
|
.es_dbg_trigger (es_dbg_trigger),
|
|
.es_dbg_data (es_dbg_data));
|
|
|
|
// processor
|
|
|
|
up_gt #(.PCORE_ID(PCORE_ID)) i_up_gt (
|
|
.gt_pll_rst (gt_pll_rst),
|
|
.gt_rx_rst (gt_rx_rst),
|
|
.gt_tx_rst (gt_tx_rst),
|
|
.up_cpll_pd (up_cpll_pd_s),
|
|
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_s),
|
|
.up_rx_out_clk_sel (up_rx_out_clk_sel_s),
|
|
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_s),
|
|
.up_tx_out_clk_sel (up_tx_out_clk_sel_s),
|
|
.rx_clk (rx_clk),
|
|
.rx_rst (rx_rst),
|
|
.rx_ext_sysref (rx_ext_sysref),
|
|
.rx_sysref (rx_sysref),
|
|
.rx_ip_sync (rx_ip_sync),
|
|
.rx_sync (rx_sync),
|
|
.rx_rst_done (rx_rst_done_extn_s[7:0]),
|
|
.rx_pll_locked (rx_pll_locked_extn_s[7:0]),
|
|
.rx_error (1'd0),
|
|
.tx_clk (tx_clk),
|
|
.tx_rst (tx_rst),
|
|
.tx_ext_sysref (tx_ext_sysref),
|
|
.tx_sysref (tx_sysref),
|
|
.tx_sync (tx_sync),
|
|
.tx_ip_sync (tx_ip_sync),
|
|
.tx_rst_done (tx_rst_done_extn_s[7:0]),
|
|
.tx_pll_locked (tx_pll_locked_extn_s[7:0]),
|
|
.tx_error (1'd0),
|
|
.drp_clk (drp_clk),
|
|
.drp_rst (drp_rst),
|
|
.drp_sel (drp_sel_s),
|
|
.drp_wr (drp_wr_s),
|
|
.drp_addr (drp_addr_s),
|
|
.drp_wdata (drp_wdata_s),
|
|
.drp_rdata (drp_rdata_s),
|
|
.drp_ready (drp_ready_s),
|
|
.drp_lanesel (drp_lanesel_s),
|
|
.drp_rx_rate (drp_rx_rate_s),
|
|
.es_sel (es_sel_s),
|
|
.es_wr (es_wr_s),
|
|
.es_addr (es_addr_s),
|
|
.es_wdata (es_wdata_s),
|
|
.es_rdata (es_rdata_s),
|
|
.es_ready (es_ready_s),
|
|
.es_start (es_start_s),
|
|
.es_stop (es_stop_s),
|
|
.es_init (es_init_s),
|
|
.es_prescale (es_prescale_s),
|
|
.es_voffset_step (es_voffset_step_s),
|
|
.es_voffset_max (es_voffset_max_s),
|
|
.es_voffset_min (es_voffset_min_s),
|
|
.es_hoffset_max (es_hoffset_max_s),
|
|
.es_hoffset_min (es_hoffset_min_s),
|
|
.es_hoffset_step (es_hoffset_step_s),
|
|
.es_start_addr (es_start_addr_s),
|
|
.es_sdata0 (es_sdata0_s),
|
|
.es_sdata1 (es_sdata1_s),
|
|
.es_sdata2 (es_sdata2_s),
|
|
.es_sdata3 (es_sdata3_s),
|
|
.es_sdata4 (es_sdata4_s),
|
|
.es_qdata0 (es_qdata0_s),
|
|
.es_qdata1 (es_qdata1_s),
|
|
.es_qdata2 (es_qdata2_s),
|
|
.es_qdata3 (es_qdata3_s),
|
|
.es_qdata4 (es_qdata4_s),
|
|
.es_dmaerr (es_dmaerr_s),
|
|
.es_status (es_status_s),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_sel_s),
|
|
.up_wr (up_wr_s),
|
|
.up_addr (up_addr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_rdata (up_rdata_s),
|
|
.up_ack (up_ack_s));
|
|
|
|
// axi interface
|
|
|
|
up_axi #(
|
|
.PCORE_BASEADDR (C_BASEADDR),
|
|
.PCORE_HIGHADDR (C_HIGHADDR))
|
|
i_up_axi (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_axi_awvalid (s_axi_awvalid),
|
|
.up_axi_awaddr (s_axi_awaddr),
|
|
.up_axi_awready (s_axi_awready),
|
|
.up_axi_wvalid (s_axi_wvalid),
|
|
.up_axi_wdata (s_axi_wdata),
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
.up_axi_wready (s_axi_wready),
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
.up_axi_bresp (s_axi_bresp),
|
|
.up_axi_bready (s_axi_bready),
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
.up_axi_araddr (s_axi_araddr),
|
|
.up_axi_arready (s_axi_arready),
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
.up_axi_rresp (s_axi_rresp),
|
|
.up_axi_rdata (s_axi_rdata),
|
|
.up_axi_rready (s_axi_rready),
|
|
.up_sel (up_sel_s),
|
|
.up_wr (up_wr_s),
|
|
.up_addr (up_addr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_rdata (up_rdata_s),
|
|
.up_ack (up_ack_s));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|