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pluto_hdl_adi/library/ip_pid_controller/component.xml

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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>ip_pid_controller</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>rst</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>rst</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.RST.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ref_speed</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ref_speed</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.REF_SPEED.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>new_motor_speed</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>new_motor_speed</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.NEW_MOTOR_SPEED.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>motor_speed</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>motor_speed</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.MOTOR_SPEED.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>kp</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>kp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.KP.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ki</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ki</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.KI.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>kd</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>kd</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.KD.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>err</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>err</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.ERR.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pwm</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pwm</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.PWM.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>speed</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>speed</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SPEED.LAYERED_METADATA">xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>ip_pid_controller</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
<spirit:displayName>Verilog Simulation</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>ip_pid_controller</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_utilityxitfiles</spirit:name>
<spirit:displayName>Utility XIT/TTCL</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_utilityxitfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>rst</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ref_speed</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>new_motor_speed</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>motor_speed</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>kp</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ki</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>kd</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>err</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>pwm</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>speed</spirit:name>
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<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>ip_pid_controller_c_addsub_v12_0_0/ip_pid_controller_c_addsub_v12_0_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>ip_pid_controller_c_addsub_v12_0_1/ip_pid_controller_c_addsub_v12_0_1.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>ip_pid_controller_mult_gen_v12_0_0/ip_pid_controller_mult_gen_v12_0_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>ip_pid_controller_div_gen_v5_1_0/ip_pid_controller_div_gen_v5_1_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>ip_pid_controller_c_counter_binary_v12_0_0/ip_pid_controller_c_counter_binary_v12_0_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs/ip_pid_controller.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/conv_pkg.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile>true</spirit:isIncludeFile>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/synth_reg.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/synth_reg_w_init.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/convert_type.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/xlclockdriver_rd.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip_pid_controller_entity_declarations.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip_pid_controller.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>ip_pid_controller_c_addsub_v12_0_0/ip_pid_controller_c_addsub_v12_0_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>ip_pid_controller_c_addsub_v12_0_1/ip_pid_controller_c_addsub_v12_0_1.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>ip_pid_controller_mult_gen_v12_0_0/ip_pid_controller_mult_gen_v12_0_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>ip_pid_controller_div_gen_v5_1_0/ip_pid_controller_div_gen_v5_1_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>ip_pid_controller_c_counter_binary_v12_0_0/ip_pid_controller_c_counter_binary_v12_0_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/conv_pkg.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile>true</spirit:isIncludeFile>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/synth_reg.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/synth_reg_w_init.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/convert_type.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/xlclockdriver_rd.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip_pid_controller_entity_declarations.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip_pid_controller.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/ip_pid_controller_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sysgen_icon_100.png</spirit:name>
<spirit:userFileType>image</spirit:userFileType>
<spirit:userFileType>LOGO</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description> This IP was generated from System Generator. All changes must be made in SysGen model. </spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ip_pid_controller_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/motor_control</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>ip_pid_controller</xilinx:displayName>
<xilinx:coreRevision>29608450</xilinx:coreRevision>
<xilinx:paymentRequired>false</xilinx:paymentRequired>
<xilinx:coreCreationDateTime>2014-04-28T13:34:48Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2013.4</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
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