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pluto_hdl_adi/library/intel
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Istvan Csomortani 103cbe73dc intel/adi_jesd204: Add support for external core clock 
In Subclass 1 mode, we need to use a separate clock (device clock) to
drive the link and transport layer of the interface. Implement the
required infrastructure for this scenario.

The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
 		2019-10-02 15:32:17 +03:00
..
adi_jesd204 intel/adi_jesd204: Add support for external core clock 2019-10-02 15:32:17 +03:00
avl_adxcfg all: Rename altera to intel 2019-06-29 06:53:51 +03:00
avl_adxcvr avl_adxcvr: Rename variables with alt_* pre-fix 2019-06-29 06:53:51 +03:00
avl_adxcvr_octet_swap library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
avl_adxphy library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
avl_dacfifo scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
axi_adxcvr intel/axi_adxcvr_up: Add device spec register 2019-10-02 08:39:01 +03:00
common intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym 2019-06-29 06:53:51 +03:00
jesd204_phy intel/jesd204_phy: Add support for external coreclkin 2019-10-02 15:32:17 +03:00
util_clkdiv scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00