zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/intel/jesd204_phy
History
Istvan Csomortani aeaefd2c1c intel/jesd204_phy: Add support for external coreclkin 
In Subclass 1 mode an external device clock (core clock) is used,
instead of the PCS output clock, to drive the link and transport layer.

Define an additional parameter, which can be used to enable clock input
port for the PHY module, which can be used as rx|tx_coreclkin source.
 		2019-10-02 15:32:17 +03:00
..
Makefile all: Rename altera to intel 2019-06-29 06:53:51 +03:00
jesd204_phy_glue.v all: Rename altera to intel 2019-06-29 06:53:51 +03:00
jesd204_phy_glue_hw.tcl library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
jesd204_phy_hw.tcl intel/jesd204_phy: Add support for external coreclkin 2019-10-02 15:32:17 +03:00