428 lines
12 KiB
Verilog
428 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad7175 (
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// adc interface (clk, data, over-range)
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adc_sdo_i,
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adc_sdi_o,
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adc_cs_o,
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adc_sclk_o,
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adc_clk_i,
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led_clk_o,
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// dma interface
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adc_clk,
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adc_enable_0,
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adc_data_0,
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adc_enable_1,
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adc_data_1,
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adc_enable_2,
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adc_data_2,
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adc_enable_3,
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adc_data_3,
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adc_valid_o,
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adc_dovf,
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adc_dunf,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rready);
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// parameters
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parameter PCORE_ID = 0;
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_ADC_DP_DISABLE = 0;
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parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
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parameter C_S_AXI_MIN_SIZE = 32'hffff;
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// adc interface (clk, data, over-range)
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input adc_sdo_i;
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output adc_sdi_o;
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output adc_cs_o;
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output adc_sclk_o;
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input adc_clk_i;
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output led_clk_o;
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// dma interface
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output adc_clk;
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output adc_enable_0;
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output [31:0] adc_data_0;
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output adc_enable_1;
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output [31:0] adc_data_1;
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output adc_enable_2;
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output [31:0] adc_data_2;
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output adc_enable_3;
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output [31:0] adc_data_3;
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output adc_valid_o;
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input adc_dovf;
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input adc_dunf;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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// internal registers
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reg [31:0] up_rdata = 'd0;
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reg up_rack = 'd0;
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reg up_wack = 'd0;
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wire adc_valid_s;
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reg adc_valid_d1;
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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// internal signals
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wire adc_status_s;
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wire up_sel_s;
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wire up_wr_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s[0:4];
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wire up_rack_s[0:4];
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wire up_wack_s[0:4];
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wire [31:0] adc_data_s;
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wire [ 1:0] adc_reg_rw_s;
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wire [31:0] adc_reg_address_s;
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wire [31:0] adc_reg_data_w_s;
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wire [31:0] adc_rx_data_s;
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wire adc_rx_data_rdy_s;
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wire adc_tx_data_rdy_s;
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wire [31:0] adc_gpio_out;
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wire clk_div_update_rdy_s;
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wire [31:0] phase_data_s;
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// signal name changes
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assign adc_clk = s_axi_aclk;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign adc_valid_o = adc_valid_s & ~adc_valid_d1;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
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up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4];
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up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4];
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adc_valid_d1 <= adc_valid_s;
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end
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end
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// channel
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axi_ad7175_channel #(
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.CHID(0),
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.DP_DISABLE (PCORE_ADC_DP_DISABLE))
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i_channel_0 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data ({8'b0, adc_data_s[23:0]}),
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.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)),
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.adc_data_out (adc_data_0),
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.adc_valid (),
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.adc_enable (adc_enable_0),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0]));
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// channel
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axi_ad7175_channel #(
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.CHID(1),
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.DP_DISABLE (PCORE_ADC_DP_DISABLE))
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i_channel_1 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (phase_data_s),
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.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)),
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.adc_data_out (adc_data_1),
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.adc_valid (),
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.adc_enable (adc_enable_1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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// channel
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axi_ad7175_channel #(
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.CHID(3),
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.DP_DISABLE (PCORE_ADC_DP_DISABLE))
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i_channel_2 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data ({8'b0, adc_data_s[23:0]}),
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.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)),
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.adc_data_out (adc_data_2),
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.adc_valid (),
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.adc_enable (adc_enable_2),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[2]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[2]),
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.up_rack (up_rack_s[2]));
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axi_ad7175_channel #(
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.CHID(4),
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.DP_DISABLE (PCORE_ADC_DP_DISABLE))
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i_channel_3 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (phase_data_s),
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.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)),
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.adc_data_out (adc_data_3),
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.adc_valid (adc_valid_s),
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.adc_enable (adc_enable_3),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[3]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[3]),
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.up_rack (up_rack_s[3]));
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// clock divider
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clk_div clk_div_i (
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.clk_i(s_axi_aclk),
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.reset_n_i(up_rstn),
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.new_div_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h40)),
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.div_i(adc_reg_data_w_s[31:0]),
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.new_phase_inc_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h41)),
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.phase_inc_i(adc_reg_data_w_s[31:0]),
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.reg_update_rdy_o(clk_div_update_rdy_s),
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.clk_o(led_clk_o),
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.phase_o(phase_data_s));
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// main (device interface)
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ad7175_if ad7175_if_i(
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.fpga_clk_i(s_axi_aclk),
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.adc_clk_i(adc_clk_i),
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.reset_n_i(~adc_rst),
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.start_conversion_i(adc_gpio_out[0]),
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.dma_data_o(adc_data_s),
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.dma_data_rdy_o(data_rd_ready_s),
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.start_transmission_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] < 8'h39)),
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.tx_data_i({adc_reg_address_s[7:0], adc_reg_data_w_s[23:0]}),
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.tx_data_rdy_o(adc_tx_data_rdy_s),
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.start_read_i(adc_reg_rw_s[0] && (adc_reg_address_s[7:0] < 8'h39)),
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.rx_data_o(adc_rx_data_s),
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.rx_data_rdy_o(adc_rx_data_rdy_s),
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.adc_sdo_i(adc_sdo_i),
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.adc_sdi_o(adc_sdi_o),
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.adc_cs_o(adc_cs_o),
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.adc_sclk_o(adc_sclk_o),
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.adc_status_o(adc_status_s));
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// common processor control
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up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status (adc_status_s),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (adc_dunf),
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.adc_clk_ratio (32'd1),
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.adc_reg_address(adc_reg_address_s),
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.adc_reg_data_r(adc_rx_data_s),
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.adc_reg_data_w(adc_reg_data_w_s),
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.adc_reg_rw(adc_reg_rw_s),
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.adc_reg_done(adc_tx_data_rdy_s | adc_rx_data_rdy_s | clk_div_update_rdy_s),
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.up_status_pn_err (1'b0),
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.up_status_pn_oos (1'b0),
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.up_status_or (1'b0),
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.delay_clk (),
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.delay_rst (),
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.delay_sel (),
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.delay_rwn (),
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.delay_addr (),
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.delay_wdata (),
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.delay_rdata (),
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.delay_ack_t (),
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.delay_locked (),
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.drp_clk (1'd0),
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.drp_rst (),
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.drp_sel (),
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.drp_wr (),
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.drp_addr (),
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.drp_wdata (),
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.drp_rdata (16'd0),
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.drp_ready (1'd0),
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.drp_locked (1'd1),
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.up_usr_chanmax (),
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.adc_usr_chanmax (8'd0),
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.up_adc_gpio_in (),
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.up_adc_gpio_out (adc_gpio_out),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[4]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[4]),
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.up_rack (up_rack_s[4]));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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