Adrian Costina 07e52b4566 m2k: Connect logic_analyzer path to clk_out instead of clk ... - this allows for the clock switching to be done inside axi_logic_analyzer core		2017-04-18 12:17:39 +02:00
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Makefile	m2k: Reduce AXI interconnect utilization	2017-04-18 12:17:39 +02:00
system_bd.tcl	M2K: initial commit	2017-01-31 16:43:40 +02:00
system_constr.xdc	m2k: Connect logic_analyzer path to clk_out instead of clk	2017-04-18 12:17:39 +02:00
system_project.tcl	remove processing order (no clock def dependency)	2017-02-22 16:02:08 -05:00
system_top.v	m2k: Updated project to use new tx path with serdes	2017-04-18 12:17:39 +02:00