zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/axi_dmac
History
Lars-Peter Clausen 92984dc802 axi_dmac: Move sync transfer start logic to the data mover 
The only two users of the data mover module both implement the same
sync-transfer-start logic. Move this into the data mover module to avoid
the duplicated code.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-07-03 13:44:34 +02:00
..
bd axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value 2018-04-24 12:49:24 +02:00
tb axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
2d_transfer.v axi_dmac: 2d_transfer: Remove resets from data path 2018-06-05 14:28:40 +02:00
Makefile axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
address_generator.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
axi_dmac_burst_memory.v axi_dmac: Remove backpressure from the source pipeline 2018-07-03 13:44:34 +02:00
axi_dmac_constr.sdc axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_constr.ttcl axi_dmac: Route destination request ID through the burst memory 2018-07-03 13:44:34 +02:00
axi_dmac_hw.tcl axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_ip.tcl axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_regmap.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac_regmap_request.v axi_dmac: Split register map into separate sub-module 2018-05-03 14:49:06 +02:00
axi_dmac_reset_manager.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac_resize_dest.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_resize_src.v axi_dmac: Remove backpressure from the source pipeline 2018-07-03 13:44:34 +02:00
axi_dmac_transfer.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
axi_register_slice.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
data_mover.v axi_dmac: Move sync transfer start logic to the data mover 2018-07-03 13:44:34 +02:00
dest_axi_mm.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dest_axi_stream.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dest_fifo_inf.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
inc_id.h axi_dmac: Fix some data width mismatches 2017-08-01 15:22:29 +02:00
request_arb.v axi_dmac: Remove backpressure from the source pipeline 2018-07-03 13:44:34 +02:00
request_generator.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
resp.h Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00
response_generator.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
response_handler.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
splitter.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
src_axi_mm.v axi_dmac: Remove backpressure from the source pipeline 2018-07-03 13:44:34 +02:00
src_axi_stream.v axi_dmac: Move sync transfer start logic to the data mover 2018-07-03 13:44:34 +02:00
src_fifo_inf.v axi_dmac: Move sync transfer start logic to the data mover 2018-07-03 13:44:34 +02:00