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pluto_hdl_adi/library/axi_dmac/tb
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Lars-Peter Clausen 0d337edbdf axi_dmac: Eliminate beat counter for the destination interfaces 
Currently both the source side and the destination side interfaces employ a
beat counter to identify the last beat in a burst.

The burst memory already has an internal last signal on the destination
side. Exporting it allows the destination side interfaces to use it instead
of having to generate their own signal. This allows to eliminate the beat
counters on the destination side and simplify the data path logic.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-07-03 13:44:34 +02:00
..
axi_read_slave.v axi_dmac: Add transfer testbenches 2018-05-03 14:49:06 +02:00
axi_slave.v axi_dmac: Add transfer testbenches 2018-05-03 14:49:06 +02:00
axi_write_slave.v axi_dmac/dma_write_tb: added data integrity check 2018-05-03 14:49:06 +02:00
dma_read_shutdown_tb axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dma_read_shutdown_tb.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
dma_read_tb axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dma_read_tb.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
dma_write_shutdown_tb axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
dma_write_shutdown_tb.v axi_dmac: Add testbenches that exercise DMA shutdown 2018-07-03 13:44:34 +02:00
dma_write_tb axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
dma_write_tb.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
regmap_tb axi_dmac: Add simple register map testbench 2018-05-03 14:49:06 +02:00
regmap_tb.v axi_dmac: made vlog pass 2018-05-03 14:49:06 +02:00
reset_manager_tb axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
reset_manager_tb.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
run_tb.sh axi_dmac: added ModelSim support to run_tb.sh 2018-05-03 14:49:06 +02:00
tb_base.v axi_dmac: Add simple register map testbench 2018-05-03 14:49:06 +02:00