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pluto_hdl_adi/library/axi_ad9361
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Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline 
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 		2022-06-28 18:06:56 +03:00
..
intel libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
xilinx libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
Makefile Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
axi_ad9361.v libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
axi_ad9361_constr.sdc library/axi_ad9361: tdd false paths 2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc axi_ad9361: Update constraints in case TDD is disabled 2021-03-04 11:13:10 +02:00
axi_ad9361_delay.tcl move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl Update Quartus Prime version from 19.3.0 to 20.1.0 2021-03-08 11:29:33 +02:00
axi_ad9361_ip.tcl library: Add link to wiki for IPs 2021-10-25 10:44:53 +03:00
axi_ad9361_rx.v libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
axi_ad9361_rx_channel.v libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
axi_ad9361_rx_pnmon.v libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
axi_ad9361_tdd.v libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
axi_ad9361_tdd_if.v libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
axi_ad9361_tx.v libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
axi_ad9361_tx_channel.v libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00