241 lines
9.1 KiB
Verilog
241 lines
9.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9625_if #(
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parameter ID = 0
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) (
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk,
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input [ 3:0] rx_sof,
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input [255:0] rx_data,
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// adc data output
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output adc_clk,
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input adc_rst,
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output [191:0] adc_data,
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output adc_or,
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output adc_status,
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output [ 15:0] adc_sref,
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input adc_sref_sync,
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input [ 3:0] adc_raddr_in,
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output [ 3:0] adc_raddr_out
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);
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// internal registers
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reg [191:0] adc_data_int = 'd0;
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reg adc_status_int = 'd0;
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reg [ 15:0] adc_sref_int = 'd0;
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reg [191:0] adc_data_cur = 'd0;
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reg [191:0] adc_data_prv = 'd0;
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reg [ 3:0] adc_waddr = 'd0;
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reg [191:0] adc_wdata = 'd0;
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reg [ 3:0] adc_raddr = 'd0;
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// internal signals
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wire [191:0] adc_rdata_s;
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wire [ 3:0] adc_raddr_s;
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wire [ 15:0] adc_sref_s;
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wire [191:0] adc_data_s;
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wire [ 15:0] adc_data_s15_s;
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wire [ 15:0] adc_data_s14_s;
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wire [ 15:0] adc_data_s13_s;
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wire [ 15:0] adc_data_s12_s;
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wire [ 15:0] adc_data_s11_s;
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wire [ 15:0] adc_data_s10_s;
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wire [ 15:0] adc_data_s09_s;
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wire [ 15:0] adc_data_s08_s;
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wire [ 15:0] adc_data_s07_s;
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wire [ 15:0] adc_data_s06_s;
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wire [ 15:0] adc_data_s05_s;
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wire [ 15:0] adc_data_s04_s;
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wire [ 15:0] adc_data_s03_s;
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wire [ 15:0] adc_data_s02_s;
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wire [ 15:0] adc_data_s01_s;
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wire [ 15:0] adc_data_s00_s;
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wire [ 31:0] rx_data0_s;
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wire [ 31:0] rx_data1_s;
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wire [ 31:0] rx_data2_s;
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wire [ 31:0] rx_data3_s;
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wire [ 31:0] rx_data4_s;
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wire [ 31:0] rx_data5_s;
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wire [ 31:0] rx_data6_s;
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wire [ 31:0] rx_data7_s;
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wire [255:0] rx_data_s;
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// nothing much to do on clock & over-range
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assign adc_clk = rx_clk;
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assign adc_or = 1'b0;
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// synchronization mode, multiple instances
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assign adc_data = adc_data_int;
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assign adc_status = adc_status_int;
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assign adc_sref = adc_sref_int;
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assign adc_raddr_out = adc_raddr;
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assign adc_raddr_s = (ID == 0) ? adc_raddr : adc_raddr_in;
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always @(posedge rx_clk) begin
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if (adc_sref_sync == 1'b1) begin
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adc_data_int <= adc_rdata_s;
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end else begin
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adc_data_int <= adc_data_s;
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end
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if (adc_sref_s != 16'd0) begin
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adc_sref_int <= adc_sref_s;
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end
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adc_data_cur <= adc_data_s;
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adc_data_prv <= adc_data_cur;
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if (adc_sref_s == 16'd0) begin
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adc_waddr <= adc_waddr + 1'b1;
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adc_raddr <= adc_raddr + 1'b1;
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end else begin
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adc_waddr <= 4'h0;
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adc_raddr <= 4'h8;
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end
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case (adc_sref_int)
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16'h8000: adc_wdata <= {adc_data_cur[179:0], adc_data_prv[191:180]};
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16'h4000: adc_wdata <= {adc_data_cur[167:0], adc_data_prv[191:168]};
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16'h2000: adc_wdata <= {adc_data_cur[155:0], adc_data_prv[191:156]};
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16'h1000: adc_wdata <= {adc_data_cur[143:0], adc_data_prv[191:144]};
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16'h0800: adc_wdata <= {adc_data_cur[131:0], adc_data_prv[191:132]};
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16'h0400: adc_wdata <= {adc_data_cur[119:0], adc_data_prv[191:120]};
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16'h0200: adc_wdata <= {adc_data_cur[107:0], adc_data_prv[191:108]};
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16'h0100: adc_wdata <= {adc_data_cur[ 95:0], adc_data_prv[191: 96]};
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16'h0080: adc_wdata <= {adc_data_cur[ 83:0], adc_data_prv[191: 84]};
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16'h0040: adc_wdata <= {adc_data_cur[ 71:0], adc_data_prv[191: 72]};
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16'h0020: adc_wdata <= {adc_data_cur[ 59:0], adc_data_prv[191: 60]};
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16'h0010: adc_wdata <= {adc_data_cur[ 47:0], adc_data_prv[191: 48]};
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16'h0008: adc_wdata <= {adc_data_cur[ 35:0], adc_data_prv[191: 36]};
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16'h0004: adc_wdata <= {adc_data_cur[ 23:0], adc_data_prv[191: 24]};
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16'h0002: adc_wdata <= {adc_data_cur[ 11:0], adc_data_prv[191: 12]};
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default: adc_wdata <= adc_data_prv;
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endcase
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end
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// samples only
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assign adc_sref_s = {adc_data_s15_s[14], adc_data_s14_s[14],
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adc_data_s13_s[14], adc_data_s12_s[14], adc_data_s11_s[14],
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adc_data_s10_s[14], adc_data_s09_s[14], adc_data_s08_s[14],
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adc_data_s07_s[14], adc_data_s06_s[14], adc_data_s05_s[14],
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adc_data_s04_s[14], adc_data_s03_s[14], adc_data_s02_s[14],
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adc_data_s01_s[14], adc_data_s00_s[14]};
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assign adc_data_s = {adc_data_s15_s[11:0], adc_data_s14_s[11:0],
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adc_data_s13_s[11:0], adc_data_s12_s[11:0], adc_data_s11_s[11:0],
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adc_data_s10_s[11:0], adc_data_s09_s[11:0], adc_data_s08_s[11:0],
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adc_data_s07_s[11:0], adc_data_s06_s[11:0], adc_data_s05_s[11:0],
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adc_data_s04_s[11:0], adc_data_s03_s[11:0], adc_data_s02_s[11:0],
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adc_data_s01_s[11:0], adc_data_s00_s[11:0]};
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// data is received across multiple lanes (reconstruct samples)
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assign adc_data_s15_s = {rx_data7_s[27:24], rx_data6_s[31:24], rx_data7_s[31:28]};
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assign adc_data_s14_s = {rx_data5_s[27:24], rx_data4_s[31:24], rx_data5_s[31:28]};
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assign adc_data_s13_s = {rx_data3_s[27:24], rx_data2_s[31:24], rx_data3_s[31:28]};
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assign adc_data_s12_s = {rx_data1_s[27:24], rx_data0_s[31:24], rx_data1_s[31:28]};
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assign adc_data_s11_s = {rx_data7_s[19:16], rx_data6_s[23:16], rx_data7_s[23:20]};
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assign adc_data_s10_s = {rx_data5_s[19:16], rx_data4_s[23:16], rx_data5_s[23:20]};
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assign adc_data_s09_s = {rx_data3_s[19:16], rx_data2_s[23:16], rx_data3_s[23:20]};
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assign adc_data_s08_s = {rx_data1_s[19:16], rx_data0_s[23:16], rx_data1_s[23:20]};
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assign adc_data_s07_s = {rx_data7_s[11: 8], rx_data6_s[15: 8], rx_data7_s[15:12]};
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assign adc_data_s06_s = {rx_data5_s[11: 8], rx_data4_s[15: 8], rx_data5_s[15:12]};
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assign adc_data_s05_s = {rx_data3_s[11: 8], rx_data2_s[15: 8], rx_data3_s[15:12]};
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assign adc_data_s04_s = {rx_data1_s[11: 8], rx_data0_s[15: 8], rx_data1_s[15:12]};
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assign adc_data_s03_s = {rx_data7_s[ 3: 0], rx_data6_s[ 7: 0], rx_data7_s[ 7: 4]};
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assign adc_data_s02_s = {rx_data5_s[ 3: 0], rx_data4_s[ 7: 0], rx_data5_s[ 7: 4]};
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assign adc_data_s01_s = {rx_data3_s[ 3: 0], rx_data2_s[ 7: 0], rx_data3_s[ 7: 4]};
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assign adc_data_s00_s = {rx_data1_s[ 3: 0], rx_data0_s[ 7: 0], rx_data1_s[ 7: 4]};
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assign rx_data0_s = rx_data_s[ 31: 0];
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assign rx_data1_s = rx_data_s[ 63: 32];
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assign rx_data2_s = rx_data_s[ 95: 64];
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assign rx_data3_s = rx_data_s[127: 96];
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assign rx_data4_s = rx_data_s[159:128];
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assign rx_data5_s = rx_data_s[191:160];
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assign rx_data6_s = rx_data_s[223:192];
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assign rx_data7_s = rx_data_s[255:224];
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// status
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status_int <= 1'b0;
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end else begin
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adc_status_int <= 1'b1;
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end
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end
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// alignment fifo
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ad_mem #(
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.ADDRESS_WIDTH(4),
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.DATA_WIDTH(192)
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) i_mem (
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.clka (rx_clk),
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.wea (1'b1),
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.addra (adc_waddr),
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.dina (adc_wdata),
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.clkb (rx_clk),
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.reb (1'b1),
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.addrb (adc_raddr_s),
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.doutb (adc_rdata_s));
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// frame-alignment
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genvar n;
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generate
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for (n = 0; n < 8; n = n + 1) begin: g_xcvr_if
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ad_xcvr_rx_if i_xcvr_if (
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.rx_clk (rx_clk),
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.rx_ip_sof (rx_sof),
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.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
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.rx_sof (),
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.rx_data (rx_data_s[((n*32)+31):(n*32)]));
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end
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endgenerate
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endmodule
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