427 lines
12 KiB
Verilog
427 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module regmap_tb;
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parameter VCD_FILE = {`__FILE__,"cd"};
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`define TIMEOUT 1000000
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`include "tb_base.v"
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localparam DMA_LENGTH_WIDTH = 24;
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localparam BYTES_PER_BEAT = 1;
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localparam DMA_AXI_ADDR_WIDTH = 32;
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localparam LENGTH_ALIGN = 2;
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localparam LENGTH_MASK = {DMA_LENGTH_WIDTH{1'b1}};
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localparam LENGTH_ALIGN_MASK = {LENGTH_ALIGN{1'b1}};
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localparam STRIDE_MASK = {{DMA_LENGTH_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};
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localparam ADDR_MASK = {{DMA_AXI_ADDR_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};
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localparam VAL_DBG_SRC_ADDR = 32'h76543210;
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localparam VAL_DBG_DEST_ADDR = 32'hfedcba98;
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localparam VAL_DBG_STATUS = 12'ha5;
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localparam VAL_DBG_IDS0 = 32'h01234567;
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localparam VAL_DBG_IDS1 = 32'h89abcdef;
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localparam AW = 11;
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localparam NUM_REGS = 'h200;
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wire s_axi_aclk = clk;
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wire s_axi_aresetn = ~reset;
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reg s_axi_awvalid = 1'b0;
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reg s_axi_wvalid = 1'b0;
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reg [AW-1:0] s_axi_awaddr = 'h00;
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reg [31:0] s_axi_wdata = 'h00;
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wire [1:0] s_axi_bresp;
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wire s_axi_awready;
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wire s_axi_wready;
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wire s_axi_bready = 1'b1;
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wire [3:0] s_axi_wstrb = 4'b1111;
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wire [2:0] s_axi_awprot = 3'b000;
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wire [2:0] s_axi_arprot = 3'b000;
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wire [1:0] s_axi_rresp;
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wire [31:0] s_axi_rdata;
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task write_reg;
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input [31:0] addr;
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input [31:0] value;
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begin
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@(posedge s_axi_aclk)
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s_axi_awvalid <= 1'b1;
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s_axi_wvalid <= 1'b1;
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s_axi_awaddr <= addr;
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s_axi_wdata <= value;
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@(posedge s_axi_aclk)
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while (s_axi_awvalid || s_axi_wvalid) begin
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@(posedge s_axi_aclk)
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if (s_axi_awready)
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s_axi_awvalid <= 1'b0;
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if (s_axi_wready)
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s_axi_wvalid <= 1'b0;
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end
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end
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endtask
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reg [31:0] expected_reg_mem[0:NUM_REGS-1];
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reg [AW-1:0] s_axi_araddr = 'h0;
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reg s_axi_arvalid = 'h0;
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reg s_axi_rready = 'h0;
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wire s_axi_arready;
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wire s_axi_rvalid;
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task read_reg;
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input [31:0] addr;
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output [31:0] value;
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begin
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s_axi_arvalid <= 1'b1;
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s_axi_araddr <= addr;
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s_axi_rready <= 1'b1;
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@(posedge s_axi_aclk) #0;
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while (s_axi_arvalid) begin
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if (s_axi_arready == 1'b1) begin
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s_axi_arvalid <= 1'b0;
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end
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@(posedge s_axi_aclk) #0;
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end
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while (s_axi_rready) begin
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if (s_axi_rvalid == 1'b1) begin
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value <= s_axi_rdata;
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s_axi_rready <= 1'b0;
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end
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@(posedge s_axi_aclk) #0;
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end
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end
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endtask
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task read_reg_check;
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input [31:0] addr;
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output match;
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reg [31:0] value;
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reg [31:0] expected;
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input [255:0] message;
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begin
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read_reg(addr, value);
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expected = expected_reg_mem[addr[11:2]];
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match <= value === expected;
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if (value !== expected) begin
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$display("%0s: Register mismatch for %x. Expected %x, got %x",
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message, addr, expected, value);
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end
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end
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endtask
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reg read_match = 1'b1;
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always @(posedge clk) begin
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if (read_match == 1'b0) begin
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failed <= 1'b1;
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end
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end
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task set_reset_reg_value;
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input [31:0] addr;
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input [31:0] value;
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begin
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expected_reg_mem[addr[AW-1:2]] <= value;
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end
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endtask
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task initialize_expected_reg_mem;
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integer i;
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begin
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for (i = 0; i < NUM_REGS; i = i + 1)
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expected_reg_mem[i] <= 'h00;
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/* Non zero power-on-reset values */
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set_reset_reg_value('h00, 32'h00040361); /* PCORE version register */
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set_reset_reg_value('h0c, 32'h444d4143); /* PCORE magic register */
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set_reset_reg_value('h10, 32'h00002101); /* Interface Description*/
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set_reset_reg_value('h80, 'h3); /* IRQ mask */
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set_reset_reg_value('h40c, 'h3); /* Flags */
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set_reset_reg_value('h418, LENGTH_ALIGN_MASK); /* Length alignment */
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set_reset_reg_value('h434, VAL_DBG_DEST_ADDR);
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set_reset_reg_value('h438, VAL_DBG_SRC_ADDR);
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set_reset_reg_value('h43c, VAL_DBG_STATUS);
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set_reset_reg_value('h440, VAL_DBG_IDS0);
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set_reset_reg_value('h444, VAL_DBG_IDS1);
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end
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endtask
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task check_all_registers;
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input [255:0] message;
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integer i;
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begin
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for (i = 0; i < NUM_REGS*4; i = i + 4) begin
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read_reg_check(i, read_match, message);
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end
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end
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endtask
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task write_reg_and_update;
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input [31:0] addr;
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input [31:0] value;
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integer i;
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begin
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write_reg(addr, value);
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expected_reg_mem[addr[AW-1:2]] <= value;
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end
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endtask
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task invert_register;
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input [31:0] addr;
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reg [31:0] value;
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begin
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read_reg(addr, value);
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write_reg(addr, ~value);
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end
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endtask
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task invert_all_registers;
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integer i;
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begin
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for (i = 0; i < NUM_REGS*4; i = i + 4) begin
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invert_register(i);
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end
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end
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endtask
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reg request_ready = 1'b0;
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wire [31:BYTES_PER_BEAT] request_dest_address;
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wire [31:BYTES_PER_BEAT] request_src_address;
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wire [DMA_LENGTH_WIDTH-1:0] request_x_length;
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wire [DMA_LENGTH_WIDTH-1:0] request_y_length;
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wire [DMA_LENGTH_WIDTH-1:0] request_dest_stride;
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wire [DMA_LENGTH_WIDTH-1:0] request_src_stride;
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wire request_last;
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reg response_eot = 1'b0;
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wire [6:0] response_measured_burst_length = 'hff;
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wire ctrl_enable;
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wire ctrl_pause;
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wire request_valid;
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wire request_sync_transfer_start;
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wire response_partial = 1'b1;
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reg response_valid = 1'b0;
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wire response_ready;
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always @(posedge clk) begin
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if (request_valid & request_ready) begin
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response_valid <= 1'b1;
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end else if (response_ready) begin
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response_valid <= 1'b0;
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end
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end
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integer i;
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initial begin
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initialize_expected_reg_mem();
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@(posedge s_axi_aresetn)
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set_reset_reg_value('h44c, 32'hxxxxxxxx);
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set_reset_reg_value('h450, 2'bX);
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check_all_registers("Initial");
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/* Check scratch */
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write_reg_and_update('h08, 32'h12345678);
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check_all_registers("Scratch");
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/* Check IRQ mask */
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write_reg_and_update('h80, 32'h0);
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check_all_registers("IRQ mask");
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/* Check transfer registers */
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write_reg_and_update('h40c, 'h7);
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write_reg_and_update('h410, ADDR_MASK);
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write_reg_and_update('h414, ADDR_MASK);
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write_reg_and_update('h418, LENGTH_MASK);
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write_reg_and_update('h41c, LENGTH_MASK);
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write_reg_and_update('h420, STRIDE_MASK);
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write_reg_and_update('h424, STRIDE_MASK);
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check_all_registers("Transfer setup 1");
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/* Check transfer registers */
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write_reg_and_update('h40c, {$random} & 'h7);
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write_reg_and_update('h410, {$random} & ADDR_MASK);
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write_reg_and_update('h414, {$random} & ADDR_MASK);
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write_reg_and_update('h418, {$random} & LENGTH_MASK | LENGTH_ALIGN_MASK);
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write_reg_and_update('h41c, {$random} & LENGTH_MASK);
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write_reg_and_update('h420, {$random} & STRIDE_MASK);
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write_reg_and_update('h424, {$random} & STRIDE_MASK);
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check_all_registers("Transfer setup 2");
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/* Start transfer */
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write_reg_and_update('h400, 'h01);
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write_reg_and_update('h408, 'h01);
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set_reset_reg_value('h428, 32'h00000000);
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set_reset_reg_value('h448, 24'h000000);
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set_reset_reg_value('h44c, 32'hxxxxxxxx);
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set_reset_reg_value('h450, 2'bX);
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check_all_registers("Transfer submitted");
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@(posedge clk) request_ready <= 1'b1;
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/* Interrupt pending */
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set_reset_reg_value('h84, 'h01);
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set_reset_reg_value('h88, 'h01);
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/* Transfer ID */
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set_reset_reg_value('h404, 'h01);
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/* Tansfer pending */
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set_reset_reg_value('h408, 'h00);
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set_reset_reg_value('h428, 32'h80000000);
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set_reset_reg_value('h448, 24'h000080);
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set_reset_reg_value('h44c, 32'h00000080);
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set_reset_reg_value('h450, 'h0);
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check_all_registers("Transfer accepted");
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@(posedge clk) response_eot <= 1'b1;
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@(posedge clk) response_eot <= 1'b0;
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/* Interrupt registers */
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set_reset_reg_value('h84, 'h01);
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set_reset_reg_value('h88, 'h01);
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set_reset_reg_value('h428, 'h00);
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set_reset_reg_value('h42c, 'h00);
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set_reset_reg_value('h44c, 32'h00000080);
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set_reset_reg_value('h450, 'h0);
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set_reset_reg_value('h448, 24'h000080);
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check_all_registers("Transfer completed");
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/* Clear interrupts */
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write_reg('h84, 'h01);
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set_reset_reg_value('h84, 'h00);
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set_reset_reg_value('h88, 'h00);
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check_all_registers("Clear interrupts 1");
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write_reg('h84, 'h02);
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set_reset_reg_value('h84, 'h00);
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set_reset_reg_value('h88, 'h00);
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check_all_registers("Clear interrupts 2");
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/* Check that reset works for all registers */
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do_trigger_reset();
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initialize_expected_reg_mem();
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write_reg_and_update('h40c, 'h00);
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set_reset_reg_value('h44c, 32'h00000080);
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check_all_registers("Reset 1");
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invert_all_registers();
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do_trigger_reset();
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write_reg_and_update('h40c, 'h00);
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set_reset_reg_value('h44c, 32'h00000080);
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check_all_registers("Reset 2");
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end
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axi_dmac_regmap #(
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.ID(0),
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.DISABLE_DEBUG_REGISTERS(0),
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.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT),
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.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT),
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.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
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.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
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.DMA_LENGTH_ALIGN(LENGTH_ALIGN),
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.DMA_CYCLIC(1),
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.BYTES_PER_BURST_WIDTH(7),
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.HAS_DEST_ADDR(1),
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.HAS_SRC_ADDR(1),
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.DMA_2D_TRANSFER(1),
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.SYNC_TRANSFER_START(0)
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) i_axi (
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.s_axi_aclk(s_axi_aclk),
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.s_axi_aresetn(s_axi_aresetn),
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.s_axi_awvalid(s_axi_awvalid),
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.s_axi_awaddr(s_axi_awaddr),
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.s_axi_awready(s_axi_awready),
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.s_axi_awprot(s_axi_awprot),
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.s_axi_wvalid(s_axi_wvalid),
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.s_axi_wdata(s_axi_wdata),
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.s_axi_wstrb(s_axi_wstrb),
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.s_axi_wready(s_axi_wready),
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.s_axi_bvalid(s_axi_bvalid),
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.s_axi_bresp(s_axi_bresp),
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.s_axi_bready(s_axi_bready),
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.s_axi_arvalid(s_axi_arvalid),
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.s_axi_araddr(s_axi_araddr),
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.s_axi_arready(s_axi_arready),
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.s_axi_arprot(s_axi_arprot),
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.s_axi_rvalid(s_axi_rvalid),
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.s_axi_rready(s_axi_rready),
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.s_axi_rresp(s_axi_rresp),
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.s_axi_rdata(s_axi_rdata),
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.ctrl_enable(ctrl_enable),
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.ctrl_pause(ctrl_pause),
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.request_valid(request_valid),
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.request_ready(request_ready),
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.request_dest_address(request_dest_address),
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.request_src_address(request_src_address),
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.request_x_length(request_x_length),
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.request_y_length(request_y_length),
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.request_dest_stride(request_dest_stride),
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.request_src_stride(request_src_stride),
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.request_last(request_last),
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.request_sync_transfer_start(request_sync_transfer_start),
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.irq(irq),
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.response_eot(response_eot),
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.response_measured_burst_length(response_measured_burst_length),
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.response_partial(response_partial),
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.response_valid(response_valid),
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.response_ready(response_ready),
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.dbg_src_addr(VAL_DBG_SRC_ADDR),
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.dbg_dest_addr(VAL_DBG_DEST_ADDR),
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.dbg_status(VAL_DBG_STATUS),
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.dbg_ids0(VAL_DBG_IDS0),
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.dbg_ids1(VAL_DBG_IDS1));
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endmodule
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