56 lines
2.1 KiB
Makefile
56 lines
2.1 KiB
Makefile
####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := jesd204_rx
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GENERIC_DEPS += ../../common/ad_pack.v
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GENERIC_DEPS += align_mux.v
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GENERIC_DEPS += elastic_buffer.v
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GENERIC_DEPS += jesd204_ilas_monitor.v
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GENERIC_DEPS += jesd204_lane_latency_monitor.v
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GENERIC_DEPS += jesd204_rx.v
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GENERIC_DEPS += jesd204_rx_cgs.v
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GENERIC_DEPS += jesd204_rx_ctrl.v
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GENERIC_DEPS += jesd204_rx_frame_align.v
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GENERIC_DEPS += jesd204_rx_lane.v
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XILINX_DEPS += bd/bd.tcl
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XILINX_DEPS += error_monitor.v
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XILINX_DEPS += jesd204_rx_constr.ttcl
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XILINX_DEPS += jesd204_rx_ctrl_64b.v
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XILINX_DEPS += jesd204_rx_header.v
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XILINX_DEPS += jesd204_rx_ip.tcl
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XILINX_DEPS += jesd204_rx_lane_64b.v
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XILINX_DEPS += jesd204_rx_ooc.ttcl
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
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XILINX_LIB_DEPS += jesd204/jesd204_common
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XILINX_LIB_DEPS += util_cdc
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XILINX_INTERFACE_DEPS += jesd204/interfaces
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INTEL_DEPS += ../../util_cdc/sync_bits.v
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INTEL_DEPS += ../../util_cdc/sync_data.v
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INTEL_DEPS += ../../util_cdc/sync_event.v
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INTEL_DEPS += ../jesd204_common/jesd204_eof_generator.v
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INTEL_DEPS += ../jesd204_common/jesd204_frame_align_replace.v
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INTEL_DEPS += ../jesd204_common/jesd204_frame_mark.v
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INTEL_DEPS += ../jesd204_common/jesd204_lmfc.v
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INTEL_DEPS += ../jesd204_common/jesd204_scrambler.v
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INTEL_DEPS += ../jesd204_common/pipeline_stage.v
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INTEL_DEPS += jesd204_rx_constr.sdc
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INTEL_DEPS += jesd204_rx_hw.tcl
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include ../../scripts/library.mk
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