Filip Gherman 929f80cd31 library/jesd204: Updated jesd to support more lanes ... Modified the maximum number of supported lanes up to 32 lanes for every JESD layer Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>		2022-08-04 13:10:53 +03:00
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bd	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
Makefile	Makefile: Fix misc makefiles from projects and library	2021-10-05 14:24:48 +03:00
jesd204_tx.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
jesd204_tx_constr.sdc	jesd204: Intel: NP12 support	2021-02-05 15:24:15 +02:00
jesd204_tx_constr.ttcl	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
jesd204_tx_ctrl.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
jesd204_tx_gearbox.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
jesd204_tx_header.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
jesd204_tx_hw.tcl	library/jesd204: Updated jesd to support more lanes	2022-08-04 13:10:53 +03:00
jesd204_tx_ip.tcl	library/jesd204: Updated jesd to support more lanes	2022-08-04 13:10:53 +03:00
jesd204_tx_lane.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
jesd204_tx_lane_64b.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
jesd204_tx_ooc.ttcl	jesd204: Add out of context constraint file for link layer cores	2021-05-14 15:39:40 +03:00