Laszlo Nagy d48b1bcdce ad9081_fmca_ebz/vck190: Expose ref clock parameter		2022-08-04 09:52:57 +03:00
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ad9081_fmca_ebz_bd.tcl	ad9081_fmca_ebz/vck190: Expose ref clock parameter	2022-08-04 09:52:57 +03:00
ad9081_fmca_ebz_qsys.tcl	ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters	2021-11-12 13:04:57 +02:00
versal_transceiver.tcl	ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx	2022-08-04 09:52:57 +03:00