961ebe0cc2
Deleted lines after endmodule and consecutive empty lines. Modified parentheses, extra spaces. Fixed indentation. Fixed parameters list to be each parameter on its line. Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com> |
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common | ||
zcu102 | ||
Makefile | ||
Readme.md |
Readme.md
AD9783-EBZ HDL Project
Here are some pointers to help you:
- Board Product Page
- Parts: Dual DAC, LVDS interface, 16-bit resolution, Sample rate up to 500MSPS
- Project Doc: https://wiki.analog.com/resources/fpga/xilinx/interposer/ad9783
- HDL Doc: https://wiki.analog.com/resources/fpga/xilinx/interposer/ad9783
- Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all