93 lines
4.3 KiB
Tcl
93 lines
4.3 KiB
Tcl
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package require qsys 14.0
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package require quartus::device
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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set_module_property NAME axi_ad9680
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set_module_property DESCRIPTION "AXI AD9680 Interface"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_ad9680
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set_module_property VALIDATION_CALLBACK info_param_validate
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL axi_ad9680
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add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
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add_fileset_file ad_perfect_shuffle.v VERILOG PATH $ad_hdl_dir/library/common/ad_perfect_shuffle.v
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add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
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add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
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add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
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add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
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add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
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add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
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add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
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add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
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add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
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add_fileset_file ad_ip_jesd204_adc_pnmon.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
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add_fileset_file ad_ip_jesd204_adc_channel.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
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add_fileset_file ad_ip_jesd204_adc_core.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
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add_fileset_file ad_ip_jesd204_adc_deframer.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
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add_fileset_file ad_ip_jesd204_adc_regmap.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
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add_fileset_file ad_ip_jesd204_adc.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
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add_fileset_file axi_ad9680.v VERILOG PATH axi_ad9680.v TOP_LEVEL_FILE
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add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc
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add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc
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add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc
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add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_rst_constr.sdc
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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adi_add_auto_fpga_spec_params
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# axi4 slave
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
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# transceiver interface
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ad_interface clock rx_clk input 1
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ad_interface signal rx_sof input 4 export
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add_interface if_rx_data avalon_streaming sink
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add_interface_port if_rx_data rx_data data input 128
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add_interface_port if_rx_data rx_valid valid input 1
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add_interface_port if_rx_data rx_ready ready output 1
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set_interface_property if_rx_data associatedClock if_rx_clk
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set_interface_property if_rx_data dataBitsPerSymbol 128
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# dma interface
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ad_interface clock adc_clk output 1
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add_interface adc_ch_0 conduit end
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add_interface_port adc_ch_0 adc_enable_0 enable Output 1
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add_interface_port adc_ch_0 adc_valid_0 valid Output 1
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add_interface_port adc_ch_0 adc_data_0 data Output 64
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set_interface_property adc_ch_0 associatedClock if_rx_clk
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set_interface_property adc_ch_0 associatedReset none
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add_interface adc_ch_1 conduit end
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add_interface_port adc_ch_1 adc_enable_1 enable Output 1
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add_interface_port adc_ch_1 adc_valid_1 valid Output 1
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add_interface_port adc_ch_1 adc_data_1 data Output 64
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set_interface_property adc_ch_1 associatedClock if_rx_clk
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set_interface_property adc_ch_1 associatedReset none
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ad_interface signal adc_dovf input 1 ovf
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