.. |
a5gt
|
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
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2017-02-17 15:21:33 -05:00 |
a5gte
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a5gte: Fixed timing violations
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2016-12-13 10:30:24 +02:00 |
a5soc
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common/a5soc- device can not run at 100M cpu clock
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2016-11-08 15:19:23 -05:00 |
a10gx
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Altera a10 devices: disable warnings regarding unused channels
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2017-03-01 11:32:17 +02:00 |
a10soc
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Altera a10 devices: disable warnings regarding unused channels
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2017-03-01 11:32:17 +02:00 |
ac701
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common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
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2016-12-09 13:54:39 +02:00 |
altera
|
altera/adrv9371x- add dacfifo
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2017-03-01 15:52:07 -05:00 |
c5soc
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c5soc- remove unused hps ports
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2016-05-09 13:54:08 -04:00 |
kc705
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daq2/all - warnings fix
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2016-08-17 10:36:00 -04:00 |
kcu105
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kcu105- added missing ethernet configurations
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2017-01-23 10:14:09 -05:00 |
microzed
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common: microzed: Add clock, reset and interrupt support
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2016-01-13 20:32:26 +01:00 |
mitx045
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version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
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2016-08-29 09:50:46 +03:00 |
vc707
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common/vc707- 2016.2 version
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2016-08-17 10:36:19 -04:00 |
xilinx
|
common: adc/dac fifo board designs
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2017-02-27 16:06:39 -05:00 |
zc702
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version_upgrade: Common ZC702 get an upgrade to 2016.2
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2016-08-26 10:20:04 +03:00 |
zc706
|
common: adc/dac fifo board designs
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2017-02-27 16:06:39 -05:00 |
zcu102
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zcu102/*- actual clock == desired clock
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2017-02-06 12:53:47 -05:00 |
zed
|
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
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2016-08-29 09:50:46 +03:00 |
Makefile
|
Makefiles: Updated Makefiles
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2015-10-23 10:44:27 +03:00 |